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Phd in Quality-of-Service-Aware Architectures for Shared Memory Chiplets in Multi-Die Systems
Research & development - Heilbronn | Just now
This PhD research investigates how shared memory chiplet architectures can be designed to provide both scalability and predictable performance for safety-critical systems.
Phd in Quality-of-Service-Aware Architectures for Shared Memory Chiplets in Multi-Die Systems
About imec Germany
Imec Heilbronn is a new regional hub pioneering open chiplet architectures that will power the next generation of automotive innovation and AI‑driven systems. Situated at the heart of the Innovation Park Artificial Intelligence (IPAI), imec Germany brings together world class semiconductor expertise and a vibrant ecosystem of AI innovation. This unique combination positions the site as a catalyst for technological breakthroughs that will shape the next generation of mobility and intelligent systems.
The Advanced Chip Design Accelerator (ACDA) is the core of our mission in Heilbronn—establishing a state of the art competence center dedicated to advanced chiplet design, system integration, and cutting edge methodologies. ACDA provides the expertise and tools needed to bridge the gap between early stage research and industrial adoption, enabling faster, safer, and more scalable deployment of chiplet based technologies in the automotive domain. Building on the foundation of imec’s Automotive Chiplet Program (ACP), ACDA extends this work into a regional accelerator that translates imec’s research leadership into practical, industry ready solutions. By combining advanced design capabilities with deep local collaboration, ACDA empowers both regional and global automotive players to derisk development, accelerate innovation cycles, and industrialize next generation chiplet platforms with confidence.
What you will do
Introduction and Motivation
The transition from monolithic System-on-Chip (SoC) designs toward multi-die and chiplet-based architectures represents a fundamental shift in modern computing systems. In current chiplet architectures, memory access is typically handled via dedicated memory interfaces and controllers attached to each compute chiplet. While this approach preserves locality and simplifies design, it scales poorly as the number of chiplets increases in a system. Replicating memory interfaces leads to excessive IO requirements, increased area overhead, and inefficient memory utilization, particularly in tightly constrained environments such as automotive platforms. As applications demand higher compute density within a single package, the traditional model of per-chiplet memory integration becomes increasingly unsustainable.
A promising alternative is the introduction of shared memory chiplets, where memory resources are centralized and logically shared across multiple dies via high-speed die-to-die interconnects. This architectural shift reduces IO duplication and improves resource utilization but fundamentally changes the nature of memory access. Instead of isolated local memory, compute chiplets must now compete for access to a common memory resource, leading to contention and increased latency variability. These challenges are particularly critical in safety-critical domains such as automotive systems, where predictable performance and strict timing guarantees are essential.
This proposal addresses the central question of how to design shared memory chiplet architectures that remain scalable while providing strong Quality-of-Service (QoS) guarantees required for safety-critical applications.
Research Objectives
The main objective of this PhD is to develop architectural principles and mechanisms that enable predictable and efficient access to shared memory in multi-die systems. The research aims to bridge the gap between scalability and performance guarantees by introducing cross-layer QoS mechanisms spanning interconnects, memory hierarchies, and system-level scheduling. More specifically, the work will investigate how shared memory chiplet architectures can be designed such that multiple compute chiplets can concurrently access memory resources without violating latency or bandwidth constraints. The goal is not only to optimize average system performance but to ensure bounded worst-case behavior, which is essential for safety-critical applications.
Another key objective is to understand and formalize the interplay between die-to-die communication and memory system behavior. In shared memory chiplet systems, performance bottlenecks are no longer confined to either the interconnect or the memory controller alone; instead, they emerge from their interaction. This requires a unified approach to QoS that extends across the entire data path—from the originating compute core, through the on-chip network and die-to-die links, to the memory chiplet and back.
Finally, the research aims to provide architectural guidelines and design trade-offs that can inform future chiplet-based system designs, particularly in domains where both high performance and strict predictability are required.
Research Approach
The proposed work is based on the hypothesis that shared memory architectures can be made predictable and scalable through coordinated design across multiple abstraction layers. To validate this hypothesis, the research will explore new architectural models in which memory chiplets are treated as first-class shared system resources, rather than passive memory endpoints.
A critical component of the work will be the design of die-to-die communication mechanisms and a chiplet memory controller/switch that support differentiated service levels. In existing chiplet systems, interconnects are typically optimized for throughput but provide limited support for prioritization or isolation. However, in a shared memory context, interference between traffic classes can lead to severe degradation of latency-sensitive workloads. This research will therefore investigate mechanisms such as traffic classification, priority-aware arbitration, and resource partitioning within die-to-die links and chiplet memory controllers, enabling predictable communication between chiplets. This is particularly relevant given that large memory transfers can block time-critical traffic in chiplet interconnects if no QoS enforcement is applied.
In parallel, the work will explore novel memory scheduling strategies tailored to shared chiplet memory. Unlike conventional DRAM controllers, which serve a relatively localized set of cores, shared memory chiplets must handle requests from multiple independent compute dies. This introduces new forms of contention and requires schedulers that can enforce fairness, isolation, and timing guarantees across distributed request sources. Particular attention will be given to the trade-offs between centralized and distributed control, as well as the interaction between memory scheduling and interconnect behavior.
The evaluation of proposed architectures will rely on system-level simulation. Workloads representing mixed-criticality scenarios—combining latency-sensitive control tasks and throughput-oriented computations—will be used to assess the effectiveness of the proposed mechanisms. Metrics will include latency distributions, bandwidth allocation, fairness, and energy efficiency.
Required Background
• Master’s degree in electrical engineering, computer science, or related field.
• Solid foundation in processor, compute systems and chiplet architecture
• Familiar with cache coherence concepts
• Experience with hardware description: VHDL/Verilog/SystemVerilog. Knowledge and understanding of RTL modelling and simulation
• Interest in hardware/software co-design and optimization.
Type of Work
• 30% architecture design
• 30% system evaluation and benchmarking
• 30% RTL development and modelling
• 10% literature review
Promotor & Daily Advisor
• Promotor: Professor Amrouch, Chair of AI Processor Design, Technical University of Munich
• Daily Advisor: Stephanie Friederich
• Location: imec Germany, Heilbronn
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