Engineering - Cambridge | More than two weeks ago
In this position, you will be part of the imec department leading pathfinding and development of next generation technologies, looking at the most advanced devices and systems. As Test Chip Architect, you will be part of the test chip and PDK Enablement (PDKE) team. The team is responsible for the design of relevant demonstrators for technology pathfinding. Your role in the team will be to architect the test chip demonstrators that will allow assessing imec advanced technologies in various areas including new memories, photonic ICs or 3D advanced packaged systems. This includes the definition and strategy of the test chip for technology assessment, the specifications of relevant test structures, the measurement and characterization strategy, the planning of the tape-out and the follow up of all the necessary tape-out qualifications. In this role, you will need to interact with both the technology teams as well as the System/Design-Technology Co-Optimization (STCO/DTCO) teams in order to drive the test chip to success.
Your responsibilities will include:
We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at our imec office in Cambridge, UK. With your talent, passion, and expertise, you’ll become part of a team that makes the impossible possible. You will have the chance to interact closely with circuit designers, device experts, and process integration engineers as well as major foundry, fabless and EDA partners in imec’s eco-system. You will help drive imec’s technology and memory roadmap to build the semiconductor memory technology of the near and far away future. Together, we shape the technology that will determine the society of tomorrow.