Physical design layout and PDK engineer
What you will do
As Physical design layout automation and verification engineer:
- You will support the imec design-to-tape-out business process.
- You will work in test chip layout design and verification and work with Cadence tools, LVS, Design rule (DR), and Design rule check (DRC), with CAD tools such as Mentor Calibre, Synopsys ICV etc.
- You will review the imec physical verification system and together with your colleagues, work on improvements.
- You will work on design automation to analyze, test and build design methodologies (e.g. PCELL generation in collaboration with physical designers using SKILL code) using a strong scripting skill to debug design automation flow.
- You will support imec tape-out activity by providing scripting skills (e.g. SKILL for PCELL generation)
- You will support the PDK development by contributing to DRC, LVS and PEX decks (SVRF coding)
What we do for you
We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.
We are proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a competitive salary with many fringe benefits.
Who you are
- We are looking for a candidate with a relevant industry experience in physical design, design verification and design automation.
- We need our new colleague to understand the physical layout design flow, create scripts and test design methodologies to support imec tape-out activities across various R&D fields including advanced logic, memory, 3D and Photonics.
- We look for experience with software development/programming in languages e.g. SKILL, SVRF, C/C++ and for experience with UNIX/Linux environments and scripting languages e.g. PERL or TCL as well as CMOS VLSI Design concepts, flows and EDA tools.
- We value drive, proactivity and an independent way of working.
- We look for a colleague with experience in collaborative projects and a passion for problem solving.
- We also need strong team working and English communication skills .