/Senior Mixed Signal Researcher

Senior Mixed Signal Researcher

Research & development - Leuven | More than two weeks ago

Enable zetta-scale HPC/AI system hardware prototype for energy-efficient HW-SW Codesign research

Memory Design Engineer

What you will do

The Compute System Architecture (CSA) unit at imec desires to build zetta-scale AI/HPC hardware and software solutions co-designed. We are backed by a broad in-house R&D expertise, creating a new AI computing paradigm that will move the industry forward for many years to come. Designed in tune with advanced silicon geometry, novel communication technology, our architecture provides high-performance AI computing solutions in reliability, security, and power consumption at scale. We analyze emerging usage models, build hardware and software prototypes for data-driven computing hardware capable of zetta-scale performance.

CSA is looking for a Memory Design Engineer to work on the development of key prototypes for advanced and novel near-memory and in-memory IP as a part of envisioned zetta-scale HPC/AI system. Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting the key prototyping effort functional in a quick manner. This role provides opportunities to work with senior technical people from Principal Engineers to Fellows on a regular basis.

  • The main responsibility of this role is to drive the design of memory subsystems of the prototype SoC:
  • Develop innovative HW, GPU and system designs to extend the state-of-the-art performance and efficiency.
  • Work with architects to resolve interesting use-cases to simulate.
  • Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
  • Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets.
  • Provide power projection for the future projects based on analysis.
  • Memory pathfinding activities and power performance area (PPA) optimization through design technology co-optimization (DTCO); product/design enablement.
  • Memory bitcell and complex periphery IC layout and automation.
  • Memory array/IP design, memory circuit innovation, testchip design/execution/validation.
  • Pre/post-Si validation/debug to enable yield and parametric tracking/ramp.
  • React and adapt to changes quickly
  • Communicate efficiently and effectively with various stakeholders.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth. 

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits. 

Who you are

  • We are looking for applicants with experience in SOC power simulation and modeling, hardware power simulation and analysis flow.
  • 3+ years of experience in Memory Design in advanced technology node.
  • MS or PhD in Computer/Electrical Engineering.
  • Design, characterization and verification of custom memory (SRAM, Register File, ROM) circuits.
  • Design trade-off of power, performance and area.
  • Design technology co-optimization.
  • Familiarity with power impact at architecture, logic design, and circuit levels.
  • Familiarity with multimedia data processing is a plus.
  • Familiarity with SOC design flow and methodology.
  • Familiarity with power simulation and power optimization.
  • Familiarity with CPU/GPU architecture is a big plus.
  • Silicon power measurement experience is a plus.
  • Strong communication skills are a pre-requisite since you will collaborate with a lot of different groups.
Who we are
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