/Postdoctoral Researcher: The role of mechanical stress in aging of advanced CMOS devices

Postdoctoral Researcher: The role of mechanical stress in aging of advanced CMOS devices

Research & development - Leuven | More than two weeks ago

Develop lifetime projection methodologies for device aging mechanisms under mechanical stress and propose optimal technology integration strategies

Postdoctoral Researcher: The role of mechanical stress in aging of advanced CMOS devices

What you will do

As of the 90nm node, CMOS technology has exploited strain engineering techniques to boost the device electrical performance by modifying the Si band structure, to enhance carrier mobility and to tune the device threshold voltage. While the role of mechanical stress for boosting the device electrical performance is well understood, its impact on device aging mechanisms such as Bias Temperature Instability (BTI) and Hot Carrier degradation (HCD) has not been subjected yet to comprehensive fundamental investigation. 

The role of mechanical stress on device reliability is expected to be enhanced in future CMOS nodes due to the adoption of novel technological solutions, as, e.g., the introduction of (Si)Ge either as a channel material, or as a sacrificial layer for the fabrication of Si nanosheets. Moreover, with the device dimensional scaling reaching its physical limits, 3D integration has been envisioned as a disruptive approach to continue increasing CMOS functionality per die area by stacking multiple transistor layers on top of each other. Unlike the traditional VLSI high-temperature fabrication flows, the reduced thermal budget allowed in 3D fabrication is unable to relax the large compressive strains in the transistor gate oxide, resulting in large oxide defect densities and suboptimal device reliability. Conversely, the fabrication of transistor stacks by layer transfer might enable new strain engineering possibilities to possibly optimize the device reliability. Therefore, the relation between fabrication thermal budget, mechanical strain in the semiconductor channel and in the oxide, and oxide defect properties needs to be thoroughly investigated. 

To gain insight into the relation, the researcher will use nanoindentation to apply external mechanical loads to devices and simultaneously measure the electrical characteristics as a function of stress time. Preliminary tests using nanoindentation as mechanical stressor demonstrated the feasibility of such measurements, but at the same time, it underlined the instability of the test setup for long reliability measurements. Therefore, one of the objectives of this post-doc will be to find solutions to improve the test methodology and instrumentation.  
Enhancing the measurement setup with the ability to heat up the sample will also be investigated. 

With the perfected mechanical/electrical stress setup, the researcher will be able to directly study the reliability of novel devices, i.e., how the device parameters change as a function of time under combined electrical and mechanical stress. Large-area devices will be used to investigate the defects’ average behavior, such as their areal density and energy distributions, while small-area devices will allow to study properties of at the single defect level, such as their individual capture and emission times. Collaboration with theorists is expected to identify the links with first-principles material properties, such as chemical bonds. Based on this, the researcher will develop lifetime projection methodologies for device aging mechanisms under mechanical stress and propose optimal technology integration strategies. 




What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.  

We are proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.  

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a competitive scholarship with many fringe benefits. 

Who you are

  • You have a PhD in electrical engineering, physics, or material sciences 
  • You have an in-depth knowledge/expertise of semiconductor devices 
  • You have working knowledge of semiconductor device reliability and surface chemistry  
  • You are experienced with mechanical design, setting up and running complex experiments, and data analysis 
  • We are looking for an inquisitive, research-oriented, hard-working, self-starting researcher 

This postdoctoral position is funded by imec through KU Leuven. Because of the specific financing statute which targets international mobility for postdocs, only candidates who did not stay or work/study in Belgium for more than 24 months in the past 3 years can be considered for the position (short stays such as holiday, participation in conferences, etc. are not taken into account).