/Postdoctoral Researcher Magnetic domain wall (DW) devices for next-generation memories

Postdoctoral Researcher Magnetic domain wall (DW) devices for next-generation memories

Research & development - Leuven | More than two weeks ago

As a post-doctoral researcher working on the conceptual assessment of DW-MRAM, your role will cover a design-technology co-optimization (DTCO) analysis to evaluate the feasibility of the proposed concept in terms of industry-relevant performance metrics.

Postdoctoral Researcher Magnetic domain wall (DW) devices for next-generation memories

What you will do

With the advent of ‘Big data’ and the concurrent evolution of computing processors, there is an ever-increasing need for scaled memories that can achieve higher densities, smaller form factors and reduced power consumption. Conventional CMOS-based memory devices such as SRAM and DRAM are found to be lacking in this regard due to increasing concerns of leakage and non-idealities in performance metrics. Furthermore, the advent of non-von Neumann-based computing has also increased the demand for memory devices with similar characteristics.

Several alternative memory technologies have been proposed and investigated in the past decade, of which Magnetoresistive Random Access Memory (MRAM) has emerged as one of the most promising solutions. At imec, several flavours of MRAM are being researched including STT-, SOT- and VCMA-MRAM. These technologies, however, rely on individual junctions to store a single bit of information, and therefore are more suited to existing computing architectures. New concepts, such as domain wall-based MRAM (DW-MRAM), are now emerging that utilize novel spintronic phenomena (such as DMI, chirality, etc) to allow the storage and movement of information on continuous magnetic tracks. This concept promises to increase further the memory density while enabling high throughput for high-bandwidth applications such as machine learning.

Circuit design innovations are key to position new memory concepts for success in the application domains of tomorrow. In this regard, an accurate assessment of futuristic/emerging device concepts is necessary early on to make sure the proposed design is competitive compared to the rest of the memory landscape. As a post-doctoral researcher working on the conceptual assessment of DW-MRAM, your role will cover a thorough design-technology co-optimization (DTCO) analysis to evaluate the feasibility of the proposed concept in terms of industry-relevant performance metrics such as power consumption, area coverage and read/write performance. This mainly involves the optimization of Memory bit-cell and array configurations based on pseudo memory pdks for high performance targets while being tolerant to the innate variability of MRAM devices for large arrays/blocks and large voltage budgets to ensure write without disturb. Furthermore, you will also evaluate the practicality of different designs (both traditional von Neumann designs and novel non-von Neumann designs) and benchmark these proposals at circuit-level with existing CMOS-based and emerging MRAM-based solutions. The final goal will also include the assessment of the technology concept on the most practical design. In addition to the memory applications, this research topic will also evaluate the DW-MRAM concept for machine learning applications due to its promise for true analog in-memory computing

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth. 

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a competitive salary with many fringe benefits. 

Who you are

  • You have a PhD in Electrical engineering, with a focus on memory design.
  • We are looking for your experience in the modelling of memory devices and building a memory pdk
  • You are aware of traditional memory subsystem organization and next generation of memory technology.
  • We value your experience with industry-standard EDA tools like Cadence/Synopsys, specifically Virtuoso design environment
  • Knowledge of other simulation tools such as COMSOL can be a positive addition, but not mandatory.
  • You are an effective and fluent communicator in English, and an enthusiastic team player who likes to collaborate. You are also open to constructive criticism and feedback for improvements. You are equally comfortable in working independently.

This postdoctoral position is funded by imec through KU Leuven. Because of the specific financing statute which targets international mobility for postdocs, only candidates who did not stay or work/study in Belgium for more than 24 months in the past 3 years can be considered for the position (short stays such as holiday, participation in conferences, etc. are not taken into account).