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/Vacatures/Performance Modeling Engineer

Performance Modeling Engineer

Research & development - Leuven | More than two weeks ago

Explore the impact of imec’s technology solutions on tomorrow’s Machine Learning and AI systems.

Performance Modeling Engineer

What you will do

System Architecture innovations are key to position imec for success in fast evolving workloads of tomorrow and to differentiate imec’s process technology innovations with system level value proposition. The Compute System Architecture Unit at imec leads research into futuristic high-performance and highly secure RISC-V CPUs to extend imec’s semiconductor research leadership deep into the next decade. This unit is also researching accelerator-based architectures for next-generation Artificial Intelligence (AI), compute-in-memory architectures and heterogeneous memory systems.  The team is responsible for architecture definition of new CPU and accelerator capabilities, analyzing emerging usage models, and building hardware and software prototypes for data-driven computing hardware. 

As we expand our research to better optimize computing, we are looking for a research engineer to contribute hands-on to the development of performance models for a high-performance RISC-V CPU-based platform. The Performance Modeling Engineer will be responsible for implementing and integrating detailed functional simulations of computer systems in close collaboration with other groups responsible for designing and developing these computer systems. In addition, the candidate will also be responsible for maintaining and improving performance simulation models with additional functionality and better user experience. He or she will work closely with partners to identify and customize infrastructure and workloads to inform and influence future technology definition.

We have an opening for a power and performance modeling engineer for future RISC-V based exascale computing systems. The candidate will be responsible for a domain specific system (ML appliance/AI, HPC) to achieve or beat its power and performance goals. The includes understanding (SOC) characterization, power and performance optimization in addition to the responsibility for identifying opportunities, drive optimization & improvements through analysis of workloads. The job requirements include but are not limited to:
  • Understanding workloads and performance maximizing techniques for a constrained power envelope.
  • System level understanding of power management flows at the hardware, firmware, and driver levels.
  • Analysis of silicon power consumption versus pre-silicon expectations and drive resolution of issues towards higher battery life (mobile), higher perf at different utilization points (datacenter).
  • Keep a tab on power estimation/measurement methodology and continuously evolve with the new power optimization techniques.
  • Responsibility for SoC-level optimization under various usage scenarios.
  • Close interface with architecture, design, and platform engineers.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.  
We are proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.  
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a competitive salary with many fringe benefits. 

Who you are

  • You have a Master’s degree in Electronics Engineering, with at least 3 years of relevant industrial experience or a PhD in EE/EC/CS.
  • Knowledge of caches / Memory management unit / DRAM / NOC is an advantage.
  • Hands on experience with modelling (functional and/or performance). Strong C++ skills / programming skills are a plus.
  • Strong debugging and analytical skills to debug modelling / performance issues.
  • You have a background of digital implementation and SoC architecture for one or more application domains (Mobile, Server, …) and can make specification for different parts of SoC in different market spaces.
  • You are driven by curiosity and motivated by working in a dynamic team.
  • You work in a structured, transparent and accurate way.
  • You are a constructive team player and enjoy sharing experiences and knowledge with colleagues.
  • Your networking skills, creativity, persistence and passion for what you do are highly valued. 
  • We are looking for your excellent communication skills in English, as you will work in a multicultural team and closely with our partners.