Memory Subsystem Architect
What you will do
System Architecture innovations are key to position imec for success in fast evolving workloads of tomorrow and to differentiate imec’s process technology innovations with system level value proposition. The Compute System Architecture Unit at imec leads research into futuristic high-performance and highly secure RISC-V CPUs to extend imec’s semiconductor research leadership deep into the next decade. This unit is also researching accelerator-based architectures for next-generation Artificial Intelligence (AI), compute-in-memory architectures and heterogeneous memory systems. The team is responsible for architecture definition of new CPU and accelerator capabilities, analyzing emerging usage models, and building hardware and software prototypes for data-driven computing hardware.
As we expand our research to better optimize computing, we are looking for a Memory Subsystem Architect to contribute hands-on to the development of functional models for innovative memory subsystems. The candidate will be responsible for implementing and integrating detailed functional simulations of computer systems in close collaboration with other groups responsible for designing and developing these computer systems. In addition, this research engineer will maintain and improve performance simulation models with additional functionality and better user experience. He or she will work closely with partners to identify and customize infrastructure and workloads to inform and influence future technology definition.
Changing the underlying technology for future compute systems not only improves energy efficiency dramatically but will also call for novel system architectures, spanning from SSD and DRAM to the compute core architectures, potentially across multiple accelerator nodes. The Memory Subsystem Architect will be part of a dynamic unit architecture team working on enabling better DL / system performance.
- Provide innovative architectural solutions to complex problems.
- Develop functional models of memory subsystem units.
- Work on performance simulators for new features / exploration of architectures.
- Validation of the models being written by figuring out corner cases and writing the architecture tests to validate the model.
- Performance analysis and debug of the unit / memory subsystem.
- Teaming up with various experts inside imec, you will explore and benchmark design and architecture trade-offs for compute system architecture for future applications.
You will be responsible for:
- Exploring novel chip and system architectures to enable technology development, leveraging imec’s computational memories.
- Modeling and simulating new architectures to analyze critical trade-offs and bottlenecks. You abstract away the lower-level details and capture the essential traits hat will determine power and performance.
- Interfacing with imec’s circuit and algorithm experts to understand requirements and constraints for computational memory arrays for machine-learning.
- Generating and securing IP.
- Keeping up-to-date on recent developments in the field. You do this by studying literature and interacting with your colleagues.
What we do for you
We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.
We are proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a competitive salary with many fringe benefits.
Who you are
- You have a Master’s degree in Electronics Engineering, with at least 3 years of relevant industrial experience or a PhD in EE/EC/CS.
- Knowledge of caches / Memory management unit / DRAM / NOC would be an advantage.
- Hands on experience with modelling (functional and/or performance). Strong C++ skills / programming skills are a plus.
- Strong debugging and analytical skills to debug modelling / performance issues.
- You have a background of digital implementation and SoC architecture for one or more application domains (Mobile, Server, …) and can make specification for different parts of SoC in different market spaces.
- You are driven by curiosity and motivated by working in a dynamic team.
- You work in a structured, transparent and accurate way.
- You are a constructive team player and enjoy sharing experiences and knowledge with colleagues.
- Your networking skills, creativity, persistence and passion for what you do are highly valued.
- We are looking for your excellent communication skills in English, as you will work in a multicultural team and closely with our partners.