'NanoCMOS (PullNano)' / 'more Moore' event: "Beyond 45nm technologies"

 

 

 

 

 

 

 

 

 

 

Welcome

Members

 

Membership

Members area

Events

Contact us

Disclaimer

 

Venue

 

Location

 

IMEC vzw
Kapeldreef 75
B-3001 Leuven, BELGIUM
http://www.imec.be/

       
 

Date

 

May 09-10, 2006

Abstract

Whereas the foremost objective of these Integrated Projects is to carry out advanced research that is breaking new ground, there is also ample attention dedicated to the development of adequate training and education modules and events in Microelectronics and Micro-technologies. These are indeed of utmost importance in order to timely educate the researchers and workforce needed tomorrow. Moreover, also the sharing of scientific and technical information with the wider community is one of the tasks of Integrated Projects. Therefore this event can be attended by the partners within the two projects but also to all those interested in the latest developments in this fascinating exploration of the CMOS technologies of tomorrow.

This event on “Beyond 45nm technologies” is set up in order to fulfil these purposes. It is conceived as a mixture of basic training (Tutorials), of dissemination of the latest results from both projects (with Advanced Presentations on CMOS modules and devices and on EUV lithography issues) and of putting the objectives and activities within both projects in a broader, world-wide perspective. A successful development of the future advanced CMOS nodes will rely on new breakthroughs in both lithography and process and device technologies. This joint organization therefore offers a unique opportunity to the researchers in both projects to get direct and adapted information about the challenges, progress and solutions in the endeavours of the colleagues in the other project. Moreover it offers also to researchers and managers in universities, research centers and companies that are not directly involved in one of these projects, a well balanced overview of the challenges and used approaches in both domains and the opportunity to meet the experts.

Basically it is built up into 4 modules: a session with 6 Tutorials on topics related to advanced CMOS and EUV-Lithography, a session with information on the objectives and status of the 2 Integrated Projects (more Moore and PullNano being the follow-up project for the current NanoCMOS), a session with 3 Invited Papers by recognized experts in these fields and finally a session with 8 advanced presentations on the major results from both projects.

Programme

May 09, 2006

 

10h15

 

Opening of the event and introductory remarks
Herman Maes, IMEC vzw

Part I: Tutorials

 

10h30

 

Tutorial 1 (nanoCMOS)
High-k materials - need and/or benefits
Stefan De Gendt, IMEC vzw

       
 

11h20

 

Tutorial 2 (moreMoore)
Metrology, characterization and simulation of Line Edge Roughness (LER)
Peter Leunissen, IMEC vzw

       
 

12h10

 

Lunch

       
 

13h10

 

Tutorial 3 (nanoCMOS)
Introduction of Advanced Process Control (APC)
Richard Oechsner, FhG-IISB

       
 

14h00

 

Tutorial 4 (nanoCMOS)
Advanced cleaning, contamination control and surface preparation
Twan Bearda, IMEC vzw

       
 

14h50

 

Break

       
 

15h20

 

Tutorial 5 (moreMoore)
Concept of ASML EUV tool - lithographic aspects
Anton Van Dijsseldonk, ASML

       
 

16h10

 

Tutorial 6 (moreMoore)
EUV multi-layer mirro imaging systems
Joseph Braat, Technical University of Delft

Part II: Project presentations

 

17h15

 

PullNano presentation
Gilles Thomas, ST Microelectronics

       
 

17h55

 

More Moore presentation
Rob Hartman, ASML

May 10, 2006

Part III: Invited speakers - benchmarking

 

08h30

 

Invited talk 1
TBD
TBD

       
 

09h20

 

Invited talk 2
Importance of EUV lithography in ASML's technology and product roadmap
Jos Benschop, ASML

       
 

10h10

 

Invited talk 3
Issues related to industrial IC processing
Alain Brochet, ST Microelectronics

       

Part IV: Advanced presentations - status of technology

 

11h30

 

Topic 1 (nanoCMOS)
Influence of TSi on the electronic properties of SON devices
Kader Souifi, CNRS/LPM

       
 

12h00

 

Topic 2 (moreMoore)
Lithograpgy simulations
Peter De Bisschop, IMEC vzw

       
 

12h30

 

Lunch

       
 

13h40

 

Topic 3 (nanoCMOS)
Introduction to semiconductor technology simulation
Jurgen Lorenz, FhG-IISB

       
 

14h20

 

Topic 4 (moreMoore)
EUV multi-layer masks - manufacturing and characterization
Etienne Quesnel, CEA-LETI

       
 

15h00

 

Topic 5 (nanoCMOS)
2D stress/strain mapping at nanometerscale in thin strained SiGe based layers
Nikolay Cherkashin, CNRS

       
 

16h00

 

Topic 6 (nanoCMOS)
High-k and metal gate: state of the art
Tom Schram, IMEC vzw

       
 

16h30

 

Topic 7 (nanoCMOS)
Actomoc EUVL mask blank defect inspection
Ulf Kleineberg, University of Bielefeld

       
 

17h00

 

Topic 8 (nanoCMOS)
Interconnect challenges and dual damascene integration of porous SiOC low-k at the 45nm node
Vincent Arnal, ST Microelectronics

Information & registration

For more information and registration, please visit: http://www.imec.be/tcmwebapp/internet/course.tcm?L=EN_GB&K=MTC&Course=AAAADGN.

Members of the 'Microsystems & Nanotechnology Network' enjoy a reduction of 25%.