How to transition from VHDL to systemC and what to gain

Venue

Objectives

The goal of our current SystemC course is the description and simulation of systems at RT level as well as at higher levels of abstraction. For VHDL designers this course can be seen as an introduction to C++ based design. After his course you will have a good knowledge of the basics of SystemC version 2.0.1.

This course does not cover HW/SW partitioning or the use of SCV library.

Programme

The 4-day course "How to transition from VHDL to systemC and what to gain" is centered on SystemC V2.0.1 syntax (through examples) while emphasizing good coding style and the link to hardware.

During the course the participants will:

• Learn how to use systemC for modeling hardware mainly at RT-level
• Learn how to write systemC testbenches in order to verify the functionality of a design prior to implementation
• Learn how to use systemC at DataFlow and Transaction Level
• How to simulate the systemC model

The course is 40% lectures, 60% hands-on.

Lecturers:
Geert Vanwijnsberghe, IMEC vzw & Bert Van Thielen, IMEC vzw

Hands on Training Course:

1. The basic building blocks
• SystemC introduction
• Why systemC, System-on-chip, What is systemC, installation
• Modules
• Definition, static and dynamic ports, Hierarchy, interconnect signals, parameterized modules
2. Modeling and verifying behavior
• Processes
• Definition, SC_METHOD, SC_THREAD, SC_CTHREAD, sensitivity lists, wait-statement, dynamic sensivity
• Simulation
• Concept of time, clocks, simulation control, systemC scheduler, testbench creation, tracing/viewing waveforms
• Co-simulation
• Basic VHDL - systemC co-simulation
3. The SystemC types
• SystemC basic types
• SystemC bit and vector types, systemC integers, casting and conversion between all types, supported operators, User defined data types
• SystemC fixed point types
• Quantization modes, overflow modes, fast fixed point types
4. Basic RT synthesis
• Based on Synopsys CoCentric systemC compiler
• Supported types / structures
5. High-level systemC modeling
• Data flow modeling
• Transaction level modeling
• Primitive and hierarchical channels

For every part of the course exercises are given to demonstrate the theory.

Information & registration

For more information and registration, please visit: http://www.imec.be/tcmwebapp/internet/course.tcm?L=EN_GB&K=MTC&Course=AAAAAAZ.

Members of the 'Microsystems & Nanotechnology Network' enjoy a reduction of 25%.