INFOS 2005 Program

INVITED PAPER
Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology
R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar and M. Radosavljevic
Intel, Hillsboro, OR, USA

45nm LSTP FET with FUSI Gate on PVD-HfO₂ with excellent drivability by advanced PDA treatment
R. Mitsuhashi(1), K. Yamamoto(1), S. Hayashi(3), A. Rothschild(2), S. Kubicek(2), A. Veloso(2), S. Van Elshocht(2), M. Jurczak(2), S. De Gendt(2), S. Biesemans(2) and M. Niwa(1)
(1)Matsushita assignee at IMEC, Leuven, Belgium
(2)IMEC, Leuven, Belgium
(3)Matsushita Electric Industrial Co., Ltd., Kyoto, Japan

Influence of TiN Metal Gate on Si/SiO₂ surface roughness in N and PMOSFETs
L. Thevenod(1), M. Cassé(1), M. Mouis(2), G. Reimbold(1), F. Fillot(1), B. Guillaumot(3) and F. Boulanger (1)
(1)CEA-LETI, Grenoble, France
(2)IMEP (CNRS/INPG/UJF JRU), Grenoble, France
(3)STMicroelectronics, Crolles, France

INVITED PAPER
Ge based high performance nanoscale MOSFETs
K.C. Saraswat, C.O. Chui, T. Krishnamohan, A. Nayfeh and P. McIntyre
(1)Stanford University, Stanford, CA, USA

Point defects at interfacial layers in stacks of (100)Ge with nm-thin HfO₂ and GeO_x(N_y) insulators probed by electron spin resonance
A. Stesmans and V.V. Afanas'ev
Katholieke Universiteit Leuven, Leuven, Belgium

Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates
B. De Jaeger(1), R. Bonzom(1,5), F. Leys(1), O. Richard(1), J. Van Steenbergen(1), G. Winderickx(1), E. Van Moorhem(1), G. Raskin(2), F. Letertre(3), T. Billon(4), M. Meuris(1) and M. Heyns(1)
(1)IMEC, Leuven, Belgium
(2)UMICORE, Olen, Belgium
(3)SOITEC, Bernin, France
(4)CEA/LETI, Grenoble, France
(5)Katholieke Universiteit Leuven, Leuven, Belgium

Impact of post-deposition-annealing on the electrical characteristics of HfO_xN_y gate dielectric on Ge substrate
C.-C. Cheng(1), C.-H. Chien(1,2), C.-W. Chen(1), S.-L. Hsu(2), M.-Y. Yang(3), C.-C. Huang(3), F.-L. Yang(3) and C.-Y. Chang(1)
(1)National Chiao-Tung University, Hsinchu, Taiwan
(2)National Nano Device Laboratory, Hsinchu, Taiwan
(3)Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan

Short minority carrier response time in HfO₂/Ge metal-insulator-semiconductor capacitors
A. Dimoulas(1), G. Vellianitis(1), G. Mavrou(1), E. Evangelou(1), K. Argyropoulos(1) and M. Houssa(2)
(1)NCSR 'DEMOKRITOS', Athens, Greece
(2)IMEC, Leuven, Belgium

Abrupt model interface for the 4H(0001)SiC-SiO₂ interface
F. Devynck, F. Giustino and A. Pasquarello
Ecole Polytechnique Federale de Lausanne (EPFL), Institute of Theoretical Physics, Institut Romand de Recherche Numerique en Physique des Materiaux (IRRMA), Lausanne,Switzerland

Investigation of simultaneous fluorine and carbon incorporation in a silicon oxide dielectric layer grown by PECVD
S. Altshuler, Y. Chakk, A. Rozenblat and A. Cohen
Intel Electronics, Kyriat Gat, Israel

The characterization of stacked α-Si/SiGe/α-Si sensing membrane
C.-M. Yang(1), C.-S. Lai(1), C.-Y. Wang(1),C.-E. Lue(1), J.-C. Chou(2), W.Y. Chung(3), D.G. Pijanowska(4)
(1)Chang Gung University, Kwei-Shan Tao-Yuan, Taiwan
(2)National Yunlin University of Science and Technology, Taiwan
(3)Chun Yuan Christian University, Chun-Li, Taiwan
(4)Polish Academy of Sciences, Warsaw, Poland

Characterization of interface state densities by photocurrent analysis: comparison of results for different insulator layers
M. Rommel(1), M. Groß(2), A. Ettinger(2), M. Lemberger(2), A.J. Bauer(1), L. Frey(1,2) and H. Ryssel(1,2)
(1 )Fraunhofer Institute of Integrated Systems and Device Technology, Erlangen, Germany
(2)University of Erlangen, Erlangen, Germany

Oxide traps characterization of 45 nm MOS transistors by gate current RTS noise measurements
F. Martinez(1), C. Leyris(1,2), G. Neau(1,2), M. Valenza(1), A. Hoffmann(1), J.C. Vildeuil(2), E. Vincent(2), F. Boeuf(2), T. Skotnicki(2), M. Bidaud(2), D. Barge(2) and B. Tavel(2)
(1)Université de Montpellier - UMR CNRS, Montpellier, France
(2)ST Microelectronics, Crolles, France

Charge trapping and detrapping in HfO₂ high-k MOS capacitors using internal photoemission
D. Felnhofer(1), E.P. Gusev(2), P. Jamison(2) and D.A. Buchanan(1)
(1)University of Manitoba, Winnipeg, MB, Canada
(2)IBM Semiconductor Research and Development Center, Yorktown Heigts, NY, USA

Stable electrochemically passivated Si surfaces by ultra thin benzene-type layers
J. Rappich(1), P. Hartig(2), N.H. Nickel(1), I. Sieber(1), S. Schulze(3) and Th. Dittrich(1)
(1)Hahn-Meitner-Institut, Berlin, Germany
(2)Universitaet Potsdam, Golm, Germany
(3)Technische Universitaet Chemnitz, Chemnitz, Germany

Impact of Al incorporation in hafnia on interface states in (100)Si/HfAl_xO_y
Y.G. Fedorenko, V.V. Afanas'ev and A. Stesmans
Katholieke Universiteit Leuven, Leuven, Belgium

Impact of H₂/N₂ annealing on interface defect densities in Si(100)/SiO₂/HfO₂/TiN gate stacks
M. Schmidt(1,3), M.C. Lemme(1), H. Kurz(1), T. Witters(2), T. Schram(2), K. Cherkaoui(3), A. Negara(3) and P.K. Hurley(3)
(1)Advanced Microelectronic Center Aachen, Aachen, Germany
(2)IMEC, Leuven, Belgium
(3)Tyndall National Institute, University College Cork, Cork, Ireland

Analysis of defects at the interface between high-k thin films and (100) silicon
B.J. Jones and R.C. Barklie
Trinity College, Dublin, Ireland

Laterally resolved electrical characterisation of high-k oxides with non-contact Atomic Force Microscopy
J.M. Sturm(1), A.I. Zinine(1), H. Wormeester(1), R.G. Bankras(2), J. Holleman(2), J. Schmitz(2) and B. Poelsema(1)
(1)Solid State Physics, MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands
(2)Semiconductor Components, MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands

Barrier permeation effects on the inversion layer subband structure and its applications to the electron mobility
G.S. Lujan(1,2), W. Magnus(1,3), B. Sorée(1), L-Å Ragnarsson(1), L. Trojman(1), S. Kubicek(1), S. De Gendt(1,2), M. Heyns(1,2) and K. De Meyer(1,2)
(1)IMEC, Leuven, Belgium
(2)Katholieke Universiteit Leuven, Leuven, Belgium
(3)Universiteit Antwerpen, Antwerpen, Belgium

Effect of the dielectric thickness and the metal deposition technique on the mobility for HfO₂/TaN NMOS devices
L. Trojman(1,2), L.-Å. Ragnarsson(1), L. Pantisano(1), G.S. Lujan(1,2), M. Houssa(1), T. Schram(1), M. Schaekers(1), A.Van Ammel(1), G. Groeseneken(1,2), S. De Gendt(1,2) and M. Heyns(1,2)
(1)IMEC, Leuven, Belgium
(2)Katholieke Universiteit Leuven, Leuven, Belgium

INVITED PAPER
Investigating physical and chemical changes in high-k gate stacks using nanoanalytical electron microscopy
A.J. Craven(1), M. MacKenzie(1), D.W. McComb(2), F.T. Doherty(1)
(1)University of Glasgow, Glasgow, UK
(2)Imperial College, London, UK

INVITED PAPER
Negative Bias Temperature Instability in CMOS devices
S. Mahapatra(1), M.A. Alam(2), P. Barath Kumar(1), T.R. Dalei(1), D. Varghese(1) and D. Saha(1)
(1)Indian Institute of Technology Bombay, Mumbai, India
(2)Purdue University, West Lafayette, IN, USA

Angle-resolved XPS study on chemical bonds in ultrathin silicon oxynitride films
S. Shinagawa(1), H. Nohira(1), T. Ikuta(2), M. Hori(2), M. Kase(2) and T. Hattori(1)
(1)Musashi Institute of Technology, Tokyo, Japan
(2)Fujitsu Ltd., Tokyo, Japan

Negative Bias Temperature Instability (NBTI) in SiO₂ and SiON gate dielectrics understood through disorder-controlled kinetics
B. Kaczer(1), V. Arkhipov(1), M. Jurczak(1) and G. Groeseneken(1,2)
(1)IMEC, Leuven, Belgium
(2)Katholieke Universiteit Leuven, Leuven, Belgium

Band alignment between (100)Si and Hf-based complex metal oxides
V.V. Afanas'ev(1), A. Stesmans(1), C. Zhao(2), M. Caymax(2), Z.M. Rittersma(3) and J.W. Maes(4)
(1)Katholieke Universiteit Leuven, Leuven, Belgium
(2)IMEC, Leuven, Belgium
(3)Philips Research Leuven, Leuven, Belgium
(4)ASMI, Leuven, Belgium

Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates
J.H. Stathis(1), R. Bolam(2), M. Yang(1), T.B. Hook(2), A. Chou(3) and G. Larosa(3)
(1)IBM Semiconductor Research and Development Center, Yorktown Heights, NY, USA
(2)IBM Microelectronics, Essex Junction, VT, USA
(3)IBM Microelectronics, Hopewell Junction, NY, USA

Characterization of high and low k dielectrica using low-energy time of flight elastic recoil detection
B. Brijs(1), T. Sajavaara(1,2), S. Giangrandi(1,2), K. Arstilla(3), A. Vantomme(2) and W. Vandervorst(1,2)
(1)IMEC, Leuven, Belgium
(2)Katholieke Universiteit Leuven, Leuven, Belgium
(3)University of Helsinki, Finland

Positive Bias Temperature Instability in nMOSFETs with ultra-thin Hf-silicate gate dielectrics
F. Crupi(1), C. Pace(1), G. Cocorullo(1), G. Groeseneken(2,3), M. Aoulaiche(2) and M. Houssa(2)
(1)DEIS, University of Calabria, Arcavacator di Rende, Italy
(2)IMEC, Leuven, Belgium
(3)Katholieke Universiteit Leuven, Leuven, Belgium

Intrinsic band edge traps in nano-crystalline HfO₂ gate dielectrics
G. Lucovsky(1), Y. Zhang(1), J. Luning(2), V.V. Afanas'ev(3), A. Stesmans(3), S. Zollner(4), D. Triyoso(4), B.R. Rogers(5) and J.L. Whitten(1)
(1)NC State University, Raleigh, NC, USA
(2)Stanford Syncrotron Research Labs, CA, USA
(3)Katholieke Universiteit Leuven, Leuven, Belgium
(4)Freescale Corp. USA
(5)Vanderbilt University, Nashville, TN, USA

Contribution of fast and slow states to Negative Bias Temperature Instabilities in Hf_xSi_(1-x)ON/TaN based pMOSFETs
M. Aoulaiche(1,2), M. Houssa(1), R. Degraeve(1), G. Groeseneken(1,2), S. De Gendt(1,2) and M.M. Heyns(1)
(1)IMEC, Leuven, Belgium
(2)Katholieke Universiteit Leuven, Leuven, Belgium

INVITED PAPER
Gate dielectrics on compound semiconductors
R. Droopad(1), M. Passlack(1), N. England, K. Rajagopalan(1), J. Abrokwah(1) and A. Kummel(2)
(1)Freescale Semiconductors, Tempe, AZ, USA
(2)University of California, La Jolla, CA, USA

LaAlO₃ films prepared by MBE on LaAlO₃(001) and Si(001) substrates
S. Gaillard(1,2), Y. Rozier(3), C. Merckling(1,2), F. Ducroquet(3), M. Gendry(1) and G. Hollinger(1)
(1)Ecole Centrale de Lyon, LEOM-UMR CNRS, Ecully, France
(2)ST Microelectronics, Crolles, France
(3)INSA de Lyon, LPM-UMR CNRS, Villeurbanne, France

Rare-Earth scandate single- and multi-layer thin films as alternative gate oxides for microelectronic applications
T. Heeg(1), M. Wagner(1), J. Schubert(1), Ch. Buchal(1), M. Boese(1), M. Luysberg(1), E. Cicerrella(2) and J.L. Freeouf(2)
(1)Forschungszentrum Jülich, Jülich, Germany
(2)Oregon Health & Sciences University, Beaverton, OR, USA

Growth of gadolinium oxide films for advanced MOS structures
R. Lupták(1), K. Fröhlich(1), M. T'apajna(1,2), K. Hušeková(1), D. Machajdík(1), M. Jergel(3) , J.P. Espinós(4) and C. Mansilla(4)
(1)Institute of Electrical Engineering, Bratislava, Slovakia
(2)STU, Bratislava, Slovakia
(3)Institute of Physics, SAS, Bratislava, Slovakia
(4)Instituto de Ciencia de Materiales de Sevilla, Sevilla, Spain

Chemically conformal deposition of SrTiO₃ thin films by Atomic Layer Deposition using conventional metal organic precursors and remote-plasma activated H₂O reactant
S.W. Lee, O.S. Kwon and C.S. Hwang
Seoul National University, Seoul, South Korea

Deposition of 60 nm thin Sr_0.8Bi_2.2Ta₂O₉ layers for application in scaled 1T1C and 1T FeRAM devices
L. Goux(1), Z. Xu(1,2), B. Kaczer(1), G. Groeseneken(1,2) and D. J. Wouters(1)
(1)IMEC, Leuven, Belgium
(2)Katholieke Universiteit Leuven, Leuven, Belgium

Accurate assessment of the time-to-failure of hyper-thin gate oxides subjected to constant electrical stress using a logistic-type model
F. Palumbo(1), E. Miranda(2) and S. Lombardo(1)
(1)CNR-IMM, Catania, Italy
(2)Universitat Autònoma de Barcelona, Bellaterra, Spain

Study of breakdown in ultrathin gate dielectrics using constant voltage stress and successive constant voltage stress
L.J. Tang(1,2), K.L. Pey(1), C.H.Tung(2), R. Ranjan(1) and W.H. Lin(3)
(1)Nanyang Technological University, Singapore
(2)Institute of Microelectronics, Singapore
(3)Chartered Semiconductor Manufacturing Ltd., Singapore

Dielectric breakdown in SiO₂ via electric field induced attached hydrogen defects
J. Tahir-Kheli (1), M. Miyata(2) and W.A. Goddard III (1)
(1)California Institute of Technology, Pasadena, CA, USA
(2)Seiko-Epson Corporation, Nagano-ken, Japan

Impact of Fowler-Nordheim and channel hot carrier stresses on MOSFETs with 2.2-nm gate oxide
S. Gerardin(1,2), A. Cester(1,2), A. Paccagnella(1,2) and G. Ghidini(3)
(1)University  di Padova, Padova, Italy
(2)INFM, Padova, Italy
(3)ST Microelectronics, Agrate Brianza, Italy

Understanding oxide degradation mechanisms in ultra-thin SiO₂ through high-speed, high-resolution in-situ measurements
S. Aresu(2), W. De Ceuninck(1,2), R. Degraeve(3), B. Kaczer(3), G. Knuyt(1) and L. De Schepper(1)
(1)Limburgs Universitair Centrum, Diepenbeek, Belgium
(2)IMEC, IMOMEC, Diepenbeek, Belgium
(3)IMEC, Leuven, Belgium

Edge and percolation effects on V_t window in nanocrystal memories
R. Gusmeroli, A.S. Spinelli, C. Monzio Compagnoni, D. Ielmini and A.L. Lacaita
Politecnico di Milano, Milano, Italy

INVITED PAPER
Advantages of HfAlON gate dielectric film for low power CMOS application in EOT=1nm and beyond technology era
A. Toriumi(1,3), T. Horikawa(1), K. Iwamoto(2), M. Kadoshima(2), W. Mizubayashi(1), T. Nabatame(1), A. Ogawa(2), H. Ota(1), H. Satake(2) and K. Tominaga(2)
(1)MIRAI/ASRC, Tsukuba, Japan
(2)MIRAI/ASET, Tsukuba, Japan
(3)The University of Tokyo, Tokyo, Japan

INVITED PAPER
Performance and new effects in advanced SOI devices and materials
F. Balestra
IMEP, Grenoble, France

PVD-HfSiON gate dielectrics with Ni-FUSI electrode for 65nm LSTP application
K. Yamamoto(1), S. Kubicek(2), A. Rothschild(2), R. Mitsuhashi(1), W. Deweerd(2), A.Veloso(2), M. Jurczak(2), S. Biesemans(2), S. De Gendt(2), S. Wickramanayaka(3), S. Hayashi(4) and M. Niwa(1)
(1)Matsushita assignee at IMEC, Leuven, Belgium
(2)IMEC, Leuven, Belgium
(3)ANELVA Co.
(4)Matsushita Electric Industrial Co., Ltd, Kyoto, Japan

Ultra-thin strained SOI substrate analysis by pseudo-MOS measurements
C. Gallon(1,3), C. Fenouillet-Beranger(2), N. Bresson(3,4), S. Cristoloveanu(3), F. Allibert(4), S. Bord(1), C. Aulnette(4), D. Delille(5), E. Latu-Romain(6,7), J.M. Hartmann(2), T. Ernst(2), F. Andrieu(2), Y. Campidelli(1), B. Ghyselen(4), I. Cayrefourcq(4), F. Fournel(2), N. Kernevez(2) and T. Skotnicki(1)
(1)STMicroelectronics, Crolles, France
(2)CEA-LETI, Grenoble, France
(3)IMEP, Grenoble, France
(4)Soitec S.A., Bernin, France
(5)Philips Semiconductor, Crolles, France
(6)Freescale Semiconductor, Crolles, France
(7)LEPMI, St. Martin d'Hères, France

Performance improvement of n-MOSFETs with constituent gradient HfO₂/SiO₂ interface
K. Iwamoto(1), A.Ogawa(1), T. Nabatame(1), H. Satake(1) and A. Toriumi(2,3)
(1)MIRAI-ASET, Tsukuba, Japan
(2)MIRAI-ASRC,AIST, Tsukuba, Japan
(3)University of Tokyo, Tokyo, Japan

Coupling effect between the front and back interfaces in thin SOI MOSFETs
A. Ohata(1), S. Cristoloveanu(1), A. Vandooren(2), M. Cassé(3) and F. Daugé(1)
(1)IMEP, Grenoble, France
(2)Freescale semiconductor, Crolles, France
(3)CEA-LETI, Grenoble, France

Effects of low temperature annealing on the ultrathin La₂O₃ gate dielectric; comparison of post deposition annealing and post metallization annealing
J.A. Ng(1), Y. Kuroki(1), N. Sugii(1), K. Kakushima(1), S.-I. Ohmi(1), K. Tsutsui(1), T. Hattori(1), H. Iwai(1)i and H. Wong(2)
(1)Tokyo Institute of Technology, Kanagawa-ken, Japan
(2)City University of Hong Kong, Kowloon, Hong Kong

INVITED PAPER
Innovative technologies for high density non-volatile semiconductor memories
R. Bez
STMicroelectronics, Agrate Brianza, Milano, Italy

Reduction of fixed charges in Atomic Layer Deposited Al₂O₃ dielectrics
J. Buckley(1), B. De Salvo(1), D. Deleruyelle(2), M. Gely(1), G.Nicotra(3), S.Lombardo(3), J.F. Damlencourt(1), Ph. Holliger(1), F.Martin(1) and S. Deleonibus(1)
(1)CEA-LETI, Grenoble, France
(2)L2MP - Université de Provence,Marseille, France
(3)CNR -IMM, Catania, Italy

Comparison on the effects of defects at Si(111) and Si(100) surface on electrical characteristics of MOS devices with HfO_xN_y gate dielectric
C.-L. Cheng, K.-S. Chang-Liao and T.-K. Wang
National Tsing Hua University, Hsinchu, Taiwan

Two-bit SONOS type Flash using a Band Engineering in the Nitride Layer
H.-C. Chien, C.-H. Kao, J.-W. Chang and T.-K. Tsai
Chung-Cheng Institute of Technology, National Defense University Tahsi, Taoyuan, Taiwan, R.O.C.

Effects of ALD HfO₂ thickness on charge trapping and mobility
J.H. Sim(1,3), S.C. Song(1), P.D. Kirsch(2), C.D. Young(1), R. Choi(1), D.L. Kwong(3), B.H. Lee(2) and G. Bersuker(1)
(1)SEMATECH, Austin, TX, USA
(2)IBM assignee at SEMATECH, Austin, TX, USA
(3)The University of Texas at Austin, TX, USA

Reproducible resistance switching characteristics of pulsed laser deposited polycrystalline Nb₂O₅
H. Sim, D. Choi, D. Lee, M. Hasan, C.B. Samantaray and H. Hwang
Gwangju Institute of Science and Technology, Korea

Electrical properties of high-k HfO₂ films on Si_1-xGe_x substrates
T.J. Park, S.K. Kim, J.H. Kim, J. Park, M. Cho, S.W. Lee, S.H. Hong and C.S. Hwang
Seoul National University, Seoul, South Korea

Al₂O₃ with Metal-Nitride Nanocrystals as a charge-trapping layer of MONOS-type nonvolatile memory devices
S. Choi(1), S.-S. Kim(1), H. Yang(1), M.Chang(1), S. Jeon(2), C. Kim(2), D.-Y. Kim(2) and H. Hwang(1)
(1)Gwangju Institute of Science and Technology, Gwanju, South Korea
(2)Samsung Advanced Institute of Technology, Suwon, Korea

Impact of high-k gate stack material with metal gates on LF noise in n- and p-MOSFETs
P. Srinivasan(1,2), E. Simoen(1), L. Pantisano(1), C. Claeys(1,3) and D. Misra(2)
(1)IMEC, Leuven, Belgium
(2)NJIT, Newark, NJ., USA
(3)Katholieke Universiteit Leuven, Leuven, Belgium

A nanoscale approach to the electrical properties of MOS memory devices with Si-nanocrystals
M. Porti(1), M. Avidano(1), M. Nafría(1), X. Aymerich(1), J. Carreras(2) and B. Garrido(2)
(1)Universitat Autònoma de Barcelona, Bellaterra, Spain
(2)Universitat de Barcelona, Barcelona, Spain

INVITED PAPER
First-principle calculations on gate/dielectric interfaces: on the origin of workfunction shifts
G. Pourtois(1), A. Lauwers(1), J. Kittl(1,2), L. Pantisano(1), B. Sorée(1), S. De Gendt(1,3), W. Magnus(1), M. Heyns(1,3) and K. Maex(1,3)
(1)IMEC, Leuven, Belgium
(2)Texas Instruments, Dallas, TX, USA
(3)Katholieke Universiteit Leuven, Leuven, Belgium

INVITED PAPER
Current status and challenges of ferroelectric memory devices
H. Kohlstedt(1), Y. Mustafa(2), A. Gerber(1), A. Petraru(1), M. Fitsilis(1), R. Meyer(1), U. Böttger(2) and R. Waser(2)
(1)Forschungszentrum Jülich, CNI, Jülich, Germany
(2)RWTH, Aachen, Germany

Metal gate work function extraction using Fowler-Nordheim tunneling techniques
G. Sjöblom(1), L. Pantisano(2), T. Schram(2), J. Olsson(1), V.V. Afanas'ev(3) and M. Heyns(2,3)
(1)Uppsala University, Uppzala, Sweden
(2)IMEC, Leuven, Belgium
(3)Katholieke Universiteit Leuven, Leuven, Belgium

Use of ferroelectric gate insulator for thin film transistors with ITO channel
E. Tokumitsu, M. Senoo and T. Miyasako
Tokyo Institute of Technology, Yokohama, Japan

Work function controllability of metal gates made by interdiffusing metal stacks with low and high work functions
T. Matsukawa, Y.X. Liu, M. Masahara, K. Ishii, K. Endo, H. Yamauchi, E. Sugimata, H. Takashima, T. Higashino, E. Suzuki and S. Kanemaru
Nanoelectronics Research Institute, AIST, Ibaraki, Japan

The electrical properties of metal-ferroelectric (PbZr_0.53Ti_0.47O₃)-Insulator-Silicon (MFIS) capacitors with different insulator materials
P.-C. Juan, Y.-P. Hu, F.-C. Chiu and J. Y.-M. Lee
Tsing-Hua University, Hsinchu, Taiwan

Ab initio study of charged states of hydrogen in amorphous SiO₂
J. Godet(1) and A. Pasquarello(2)
(1)Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
(2)Institut Romand de Recherche Numérique en Physique des Matériaux (IRRMA), Lausanne, Switzerland

MIM Capacitors using amorphous high-k PrTi_xO_y dielectrics
Ch. Wenger, R. Sorge, T. Schroeder, A.U. Mane, G. Lippert, G. Lupina, J. Dabrowski, P. Zaumseil and H.-J. Muessig
IHP Microelectronics, Frankfurt / Oder, Germany

Oxygen vacancies in amorphous silica: structure and distribution of properties
P.V. Sushko, S. Mukhopadhyay, A.M. Stoneham and A.L. Shluger
University College London, London, UK

Low temperature crystallized Ta₂O₅/Nb₂O₅ bi-layers integrated into RIR capacitor for 60nm generation DRAM and beyond
K. Cho(1), J. Lee(1), J.-S. Lim(1), H.J. Lim(1), J. Lee(2), S. Park(2), C.-Y. Yoo(1), S.-T. Kim(1), U-I. Chung(1) and J.-T. Moon(1)
(1)Samsung Electronics Co., Ltd., Gyeonggi-Do, South Korea
(2)Samsung Advance Institute of Technology, South Korea

INVITED PAPER
Recent developments on flash memory reliability
D. Ielmini(1), A.S. Spinelli(1) and A.L. Lacaita(1,2)
(1)Politecnico di Milano, Milano, Italy
(2)IFN-CNR, Milano, Italy

INVITED PAPER
Challenges in the implementation of low-k dielectrics in the back-end of line
R.J.O.M. Hoofman(1), G.J.A.M. Verheijden(1), J. Michelon(1), F. Iacopi(2), Y. Travaly(2), M.R. Baklanov(2), Zs. Tokei(2) and G. Beyer(2)
(1)Philips Research Leuven, Leuven, Belgium
(2)IMEC, Leuven, Belgium

Device Degradation Model for SONOS based on anode hole fluence
J.H. Yi(1), S.D. Lee(2), J.H. Ahn(2), H. Shin(2), Y.J. Park(1) and H.S. Min(1)
(1)Seoul National University, Seoul, Korea
(2)Hynix Semiconductor Inc., Kyoung-Ki, Korea

Bias-stress-induced evolution of the dielectric properties of porous-ULK/ copper advanced interconnects
C. Guedj(1), X. Portier(2), F. Mondon(1), V. Arnal(3), J.F. Guillaumond(1,3), L. Arnaud(1), J.P. Barnes(1), V. Jousseaume(1), A. Roule, S. Maitrejean(1), L.L. Chapelon(3), G. Reimbold(1), J. Torres(3) and G. Passemard(3)
(1)CEA-LETI, Grenoble, France
(2)SIFCOM-ISMRA, Caen, France
(3)STMicroelectronics, Crolles, France

New charge pumping model for the extraction of the spatial trap distribution in the nitride layer of SONOS devices
A. Arreghini(1), F. Driussi(1), D. Esseni(1), L. Selmi(1), M.J. van Duuren(2) and R. van Schaijk(2)
(1)DIEGM - University of Udine, Udine, Italy
(2)Philips Research Leuven, Leuven, Belgium

Repair and capping of porous MSQ films using chlorosilanes and supercritical CO₂
B. Xie, L. Choate and A.J. Muscat
University of Arizona, Tuscon, AZ, USA

INVITED PAPER
Breakdowns in high-k gate stacks of nano-scale CMOS devices
K.L. Pey(1), R. Ranjan(1), C.H. Tung(2), L.J. Tang(2), V.L. Lo(1), K.S. Lim(1), T.A/L Selvarajoo(1) and D.S. Ang(1)
(1)Nanyang Technological University, Singapore
(2)Institute of Microelectronics, Singapore

INVITED PAPER
Multiple gate devices: advantages and challenges
T. Poiroux(1), M. Vinet(1), O. Faynot(1), J. Widiez(1,2), J. Lolivier(1), T. Ernst(1), B. Previtali(1) and S. Deleonibus(1)
(1)LETI-CEA, Grenoble, France
(2)STMicroelectronics, Crolles, France

Investigation on trapping and detrapping mechanisms in HfO₂ films
J. Mitard(1,2), C. Leroux(2), G. Ghibaudo(3), G. Reimbold(2), X. Garros(2), B. Guillaumot(1) and F. Boulanger(2)
(1)ST Microelectronics, Crolles, France
(2)CEA-LETI, Grenoble, France
(3)IMEP, Grenoble, France

Effective Mobility in FinFET Structures with HfO₂ and SiON Gate Dielectrics and TaN Gate Electrode
T. Rudenko(1), N. Collaert(2), S. De Gendt(2), V. Kilchytska(3), M. Jurczak(2) and D. Flandre(3)
(1)National Academy of Sciences of Ukraine, Kiev, Ukraine
(2)IMEC, Leuven, Belgium
(3)Katholieke Universiteit Leuven,Leuven, Belgium

Properties and dynamic behavior of electron traps in HfO₂/SiO₂ stacks
C.Z. Zhao(1), M.B. Zahid(1), J.F. Zhang(1), G. Groeseneken(2,3), R. Degraeve(2) and S. De Gendt(2,3)
(1)John Moores University, Liverpool, UK
(2)IMEC, Leuven, Belgium
(3)Katholieke Universiteit Leuven, Leuven, Belgium

Electron mobility in multi-FinFET with a (111) channel surface fabricated by orientation-dependent wet etching
Y.X. Liu, E. Sugimata, M. Masahara, K. Endo, K. Ishii, T. Matsukawa, H. Takashima, H. Yamauchi and E. Suzuki
National Institute of Advanced Industrial Science and Technology, Japan

HfO₂/Spacer-interface breakdown in HfO₂ high-k/poly-silicon gate stacks
R. Ranjan(1), K.L. Pey(1), C.H. Tung(2), L.J. Tang(1,2), B. Elattari(3), T. Kauerauf(3,4), G. Groeseneken(3), R. Degraeve(3), D.S. Ang(1) and L.K. Bera(2)
(1)Nanyang Technological University, Singapore
(2)Institute of Microelectronics, Singapore
(3)IMEC, Leuven, Belgium
(4)Katholieke Universiteit Leuven, Leuven, Belgium

Organic field effect transistor based on a novel soluble pentacene precursor and operating at low voltage
D. Zander(1), N. Hoffmann(2), K. Lmimouni(3), S. Lenfant(3), C. Petit(1) and D. Vuillaume(3)
(1)Centre de recherche en STIC, UFR Sciences, Reims, France
(2)CNRS, Reims, France
(3)CNRS, Villeneuve d'Ascq, France

Thickness-dependent power-law of dielectric breakdown in ultrathin NMOS gate oxides
A. Hiraiwa and D. Ishikawa
Hitachi, Tokyo, Japan

Inelastic tunneling spectra of an alkyl self-assembled monolayer using a MOS tunnel junction as a test-bed
C. Petit(1), G. Salace(1) and D. Vuillaume(2)
(1)Université de Reims, France
(2)CNRS, Villeneuve d'Ascq, France

INVITED PAPER
Ab-initio simulations on growth and interface properties of epitaxial high-k oxides on silicon
C.J. Först(1,2), C.R. Ashman(1), K. Schwarz(2) and P.E. Blöchl(1)
(1)Clausthal University of Technology, Clausthal-Zellerfeld, Germany
(2)Vienna University of Technology, Vienna, Austria

INVITED PAPER
Novel fabrication process to realize ultra-thin (EOT=0.7 nm) and ultra-low-leakage SiON gate dielectrics
D. Matsushita, K. Muraoka, K. Kato, Y. Nakasaki, S. Inumiya, K. Eguchi and M. Takayanagi
Toshiba Corporation, Kanagawa, Japan

Point Defects in HfO₂ high K gate oxide
K. Xiong and J. Robertson
Cambridge University, Cambridge, UK

An approach to modeling of silicon oxidation in a wet ultra-diluted ambient
A. Kovalgin, A. Hof and J. Schmitz
University of Twente, Enschede, The Netherlands

Ab initio modelling of structure and defects at the Si/HfO₂ interface
J. Gavartin(1), L. Fonseca(2), G. Bersuker(3) and A. Shluger(1)
(1)University College London, London, U.K.
(2)Freescale Semiconductors, Brasil
(3)International Sematech, Austin, TX, USA

Comparison of electric properties of ultra-thin thermal and plasma nitrided silicon oxides with different post-deposition treatments using C-AFM
W. Polspoel(1), W. Vandervorst(1,2) and J. Pétry(3)
(1)IMEC, Leuven, Belgium
(2)Katholieke Universiteit Leuven, Leuven, Belgium
(3)Philips Research Leuven, Leuven, Belgium

Single Hf atoms in the ultrathin SiO₂ interlayer between HfO₂ dielectric and Si substrate: how do they modify the interface?
S. Rashkeev(1,2), K. van Benthem(1), S.T. Pantelides(1,2) and S.J. Pennycook(1)
(1)Oak Ridge National Laboratory, Oak Ridge, TN, USA
(2)Vanderbilt University, Nashville, TN, USA

On the trap generation rate in ultrathin SiON under Constant Voltage Stress
R. Degraeve(1), B. Kaczer(1), Ph. Roussel(1) and G. Groeseneken(1,2)
(1)IMEC, Leuven Belgium
(2)Katholieke Universiteit Leuven, Leuven, Belgium

Infrared properties of ultrathin oxides on Si(100)
F. Giustino(1) and A. Pasquarello(2)
(1)Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland
(2)Institut Romand de Recherche Numérique en Physique des Matériaux (IRRMA), Lausanne, Switzerland

Polarity dependent generation of gate-side and substrate-side oxide border traps in nitrided gate oxides
M.F. Beug(1,2), R. Ferretti(2) and K.R. Hofmann(2)
(1)Tyndall National Institute (NMRC), Cork, Ireland
(2)University of Hannover, Hannover, Germany

INVITED PAPER
Semiconductor and insulator nanostructures: challenges and opportunities
C.V. Cojocaru, F. Ratto, C. Harnagea, A. Pignolet and F. Rosei
University of Québec, Varennes, QC, Canada