ESSCIRC 2000
26th European Solid-State Circuits Conference
Stockholm, Sweden, 19-21 September 2000
[Return to Start]
[Analogue Filters]
[Analogue Integrated Circuits]
[Data Converters]
[Digital Systems and Signaling]
[Logic Circuits]
[Memories]
[PLL and Synthesizers]
[RF Circuits]
[Sensors and Imagers]
[Telecom.]
[VCO]
PLL and Synthesizers
A 12GHz /128 frequency divider in 0.25µm CMOS
De Muer B., K.U.Leuven
A 2 GHz Delta-Sigma Fractional-N Frequency Synthesizer in 0.35µm CMOS
Ahola R., Helsinki University of Technology
A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Wireless Receivers
Luong H.C., Hong Kong University of Science & Technology
A 500MHz Supply Noise Insensitive CMOS PLL with a Voltage Regulator using DC-DC Capacitive Converter
Lee C.-H., Conexant Systems, Inc.
A Novel Structure for DCO PLLs with Equivalent 16 Bit Digital Phase Quantization, Digital Loop Filter and 18ps Long-term Jitter
Da Dalt N., Infineon Technologies
An 18-mW 2.5-GHz/900-MHz BiCMOS Dual Frequency Synthesizer with < 10-Hz RF Carrier Resolution
Rhee W., Conexant Systems, Inc.
An Analogue Delay Line for Virtual Clock Enhancement in DDS
Richter R., TU Dresden
Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise
Larsson P., Bell Labs, Lucent Technologies
New Fast-Lock PLL for mobile GSM GPRS applications
Memmler B., Infineon Technologies
[Return to Start]
[Analogue Filters]
[Analogue Integrated Circuits]
[Data Converters]
[Digital Systems and Signaling]
[Logic Circuits]
[Memories]
[PLL and Synthesizers]
[RF Circuits]
[Sensors and Imagers]
[Telecom.]
[VCO]
ESSCIRC 2000