BANDIT


 Embedding Analog-to-Digital Converters on Digital Telecom ASICs


Summary

The goal of BANDIT is to develop a general design methodology for embedding high-speed analog/digital converters (ADCs) on large digital telecom ASICs, with special attention to the problems caused by mixed-signal integration. Techniques will be investigated to analyze and model digital noise generation and its impact on ADC performance. Design techniques will be developed to reduce the noise generation as well as the impact of digital noise on the performance of the ADC. The developed methodologies will be demonstrated and evaluated by means of an integrated circuit design for an industrial telecom application.

In order to use the technology scaling of CMOS processes more and more functionality, both analog and digital, has to be integrated in CMOS. By solving the noise coupling problems with appropriate design techniques, future products will benefit from smaller size, better reliability, lower cost and higher integration, eventually leading to systems on a chip (SOCs). This project focuses on embedding a high-speed wideband ADC on a large digital telecom ASIC. However a number of the methodologies being investigated in this project are more generally applicable to the integration of other analog blocks of mixed-signal receivers (as well as transmitters) or even mixed-signal ASICs in application domains other than telecom.

Main Objectives:

  1. Development of a simulation/analysis methodology to investigate the impact of substrate switching noise generated by digital circuits on the performance of analog circuits embedded on the same substrate. Emphasis is on the modeling of the noise generated by a complex digital circuit and on the modeling of the impact of substrate noise on the performance of analog circuits.
  2. Development of design techniques to reduce the substrate noise coupling in mixed-signal ASICs. Design techniques will be investigated to reduce the noise generated by a large digital circuit. At the same time analog design techniques and ADC architectures for reduced noise sensitivity will be developed.


Project partners
 
 
Coordinator IMEC vzw, Leuven, Belgium
Partner K.U.Leuven, Belgium
Partner Ericsson Radio Systems, Sweden



Project schedule

Start: September, 1998
Duration: 3 years