The tunnel field-effect transistors (TFETs) are promising successors of metal-oxide-semiconductor (MOS) FETs due to their potential for sub-60mV/dec subthreshold swing. Such a reduced swing is a necessary requirement for the ultralow power, ultralow voltage operation of the next generation of transistors. This year, other device configurations have been re-evaluated, like the nano-electromechanical (NEM)-based devices, super-steep subthreshold-slope complementary MOSFETs and other impact ionization-based devices. The conclusion is that the TFET is still the most promising device both due to its strong similarity with the MOSFET configuration, which allows significant re-use of the MOSFET expertise, and due to the absence of reliability issues with the TFET. At the same time, it is recognized that the full potential of the TFET is not yet uncovered and that the ongoing optimization of the TFET configuration is very important.

Electrical characterization of horizontal multiple-gate (MuG) tunnel-FETs

We have shown the impact of process parameters on the electrical performance of complementary multi-gate tunneling field-effect transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard CMOS processing P20071, C20726, C20868.

Firstly, the impact of the gate oxide thickness on the tunneling performance is analyzed and compared with technology computer aided design (TCAD) simulations. The reduction of the gate dielectric thickness is beneficial for the TFETs, see fig. 1. However, further scaling of the gate dielectric thickness will be a challenge due to increased gate leakage. Secondly, different implant doping conditions are investigated. The electrical results obtained for the different splits are summarized in fig. 2, and fig. 3 for wide and narrow fins. For wide fins, the impact of the doping conditions is still marginal (less than one decade). This indicates that the implantation is not able to guarantee enough abrupt profile at the tunneling junction. 2-Dimensional (2D) TCAD simulations show that not only the doping concentration but also the doping profile and gradient are important parameters for improving the tunneling current. In particular, in case of a graded junction, the performance degradation due to the lowering of the doping concentration is reduced, as shown in fig. 4. Lastly, three different annealing conditions are compared: spike anneal, sub-ms laser anneal (LA) and low-temperature anneal for solid phase epitaxy regrowth (SPER). The impact of the anneal conditions reveals that for p-type TFETs with implanted As doping, the LA and spike anneals lead to a similar profile because of the low As diffusivity. Moreover, they do not significantly impact the performance. On the other hand, the tunneling current can be greatly increased in the case of SPER anneal as shown in fig. 5. This is due to the silicide encroachment induced by residual defects (defect piping) at the junction, which is highlighted in the transmission electron microscopy (TEM) cross-section images in fig. 6. A record drive current of 46μA/μm at VDD of -1.2V and IOFF of 5pA/μm for Si pTFETs is reported for narrow fins. The high on-current is believed to be due to either an enhanced electric field caused by silicide encroachment and dopant segregation or to tunneling directly from the silicide into the silicon channel. Temperature measurements also show that the current is due to different transport mechanisms at different gate biases. Temperature measurements and TCAD simulations both confirm, the presence of trap-assisted tunneling (TAT) is mainly responsible for the degradation of the subthreshold swing, see fig. 7.

Figure 1

Figure 1: Transfer characteristics for pTFETs with 2nm and 4nm HfO2 for Wfin 250nm, LG 150nm and Nfin 5.

Figure 2

Figure 2: Table 1: Description of implant conditions splits A, B, C and D. The energy used is 10keV for all the splits.

Figure 3

Figure 3: Tunneling current for different annealing and implant conditions listed in table 1. Trends for narrow fins (red), Wfin 20nm, and wide fins (blue), Wfin 250nm, are plotted. The values are extracted at VGS of -1.5V.

Figure 4

Figure 4: Simulated input characteristics for abrupt profile and 1D-graded profile along the channel as well as two different doping concentrations. The graded profile is a Gaussian profile with an average gradient of about 6nm/decade.

Figure 5

Figure 5: pTFET IDS-VGS for wide fins (Wfin=250nm) and for three different annealing conditions.

Figure 6

Figure 6: TEM cross-section images of the devices after SPER anneal. Silicide encroachment is present in and defects are visible at the interface between the n+ region and the channel region.

Figure 7

Figure 7: pTFET IDS-VGS characteristics for different temperatures. Three regions are marked corresponding to three different transport mechanisms activated at different gate voltages. The swing is stabilized below 200K with a value of 40mV/dec (SPER anneal, Wfin 500nm).

Integration and physical analysis of vertical nanowire TFETs

This year, a new integration flow was also introduced to develop complementary heterojunction vertical TFETs and a new mask set was designed for its proof of concept. Indeed, to improve the device performance, it is necessary to use a lower bandgap material at the tunneling junction. In addition, to maintain the low off-state current and Si-compatible gate dielectric, a heterojunction at the source channel is preferred. On the other hand, for circuit compatibility, a complementary solution is needed, featuring different source materials, such as Ge for the n-type TFET and III-V materials for the p-type TFET. Therefore, a new integration scheme was proposed to co-integrate heterojunction n- and p-TFETs in a relatively simple approach, based on replacement of the source. We distinguish here a replacement -first approach from a replacement-last approach PA5.

In both approaches, a dummy source is deposited prior to the nanowire (NW) etch and is replaced later on during device processing by the appropriate source material for n- and p-type TFETs. For the source replacement-first, the replacement of the dummy source occurs after the NW etch and oxide encapsulation, whereas for the source replacement-last, this takes place after the gate etch and spacer formation. The source replacement-first approach was our main focus this year. In this integration, the dummy source (for example, poly-SiGe) is removed by HCl etch in an epi-reactor selective to the encapsulating oxide and the Si channel. This is followed in-situ by selective epitaxy growth of the suitable source material ((Si)Ge, III-V). The latter is first performed on one type of TFET while protecting the other type of TFET by a source hardmask, see fig. 8.

Figure 8

Figure 8: Schematic description of the complementary source replacement-first process flow for vertical hetero junction TFET integration.

The process modules needed for this integration scheme are currently being implemented in the 200mm processing line using the new mask set. Recent results on the source replacement module are shown in fig. 9.

Figure 9

Figure 9: Scanning electron microscopy (SEM) cross-sections of vertical NWs after (a) the dummy source etch back selectively to oxide and Si and (b) SiGe selective growth.

The doping profile (peak concentration, gradient and position with respect to the gate) is a very important parameter impacting the performance of TFETs. It is therefore very important to have a reliable technique for analyzing quantitatively the active carrier distribution inside the NW. Scanning spreading resistance microscopy (SSRM) techniques which allows 2D quantitative carrier profiling was applied successfully to our surrounded gate NWs C20350. This enables us to investigate the influence of the NW diameter and doping method onto the active dopant distribution and its impact on the device performance. When the top source is formed by 45° tilt implantation, two implantation pockets are clearly visible for wide wires, while these pockets tend to merge for narrower wires, see fig. 10. On the other hand, when the source is formed by in-situ doped epitaxial growth, the doping profile in the source is rather uniform across the wire diameter and does not vary significantly for different wire dimensions. The correlation between the doping profile and the measured electrical performance is now under investigation.

Figure 10

Figure 10: 2D-distribution of active dopants for NW diameters of 400nm (a), 300nm (b), 200nm (c) and 100nm (d).

Synthesis and characterization of III-V nanowires

Semiconducting NWs offer the possibility of both a paradigm shift in device assembly (bottom-up vs. top-down) and new physics to be exploited for added functionalities (e.g. quantum confinement effects). The monolithic integration of III-V semiconductors in non-polar semiconducting structures (typically group-IV Si or Ge) would allow the combination of properties of both materials in a single IC. Moreover, they open a new field of applications, e.g. by harmonizing optoelectronics and logic on the same IC. Although in some cases the lattice mismatch between the III-V semiconductor and Si can be significant (e.g. ~11% for the InAs/Si system), the growth of high-aspect ratio nanostructures such as NWs allows for a lesser extent of stress occurrence at the interface and the possibility to employ conventional planar technology. By adopting bottom-up, CMOS-compatible technology routes, it is possible to exploit the peculiar electronic and optical properties of III-V semiconductors, in many ways superior to those of Si (larger carrier mobilities, direct bandgap option, quantum confinement effects). In addition, the use of these 1-dimensional (1D) nano sized objects, whether belonging to the III-V or IV group, paves the way for aggressive downscaling as required by the international technology roadmap for semiconductors (ITRS) and is indeed a valid candidate in view of the 16nm node challenge (and beyond). Another interesting perspective for III-V semiconductors when tailored in low-dimensional nanostructures, let alone a stimulus for imec's cross-talk among different activities, is more specifically represented by the replacement of the Si source of a monolithic, all-Si p-TFET by an In1-xGaxAs contact. This would lead to a more efficient device performance by boosting its Ion.

Here at imec, GaAs and InAs were successfully grown in NW form on homo- and hetero-epitaxial substrates, see fig. 11. One series of experiments resulted in surface-bound InAs NWs successfully grown by metal-organic chemical-vapor deposition (MOCVD) on (111)-oriented, patterned Si substrates. A ~50nm oxide/nitride hardmask on 1×1cm2 Si substrates was patterned with <100nm hole features by conventional litho/etch processing. Samples were then loaded into the MOCVD reactor to allow for NW growth. Trimethylindium (TMI) and tertiarybutylarsine (TBA) carried by a H2 flow were employed as III- and V-precursors, respectively. After exposing the substrate to the growth atmosphere for 20min at ~600°C, <100nm InAs NWs were found to grow along the (111) direction and crystallize in a six-fold symmetry as evidenced from the hexagonal cross-section. The challenge for NW growth is twofold: to guarantee the 1D character of the nanostructure grown and to ensure that the desired crystalline structure is achieved. This is accomplished by precise tuning of the growth parameters, although substrate patterning and preparation for NW growth play a critical role as well. Test structures where GaAs NW result, homo-epitaxially grown on GaAs substrates, were also produced by following a route similar to that described for InAs NW growth; TMI was replaced by trimethylgallium (TMG) and the growth temperature was increased to ~780°C. Transmission electron microscopy, Raman spectroscopy, x-ray diffraction were performed to assess the crystalline quality of the InAs and GaAs nanostructures grown.

Figure 11

Figure 11: SEM images of arrays of vertical (a) GaAs NWs grown homo-epitaxially by MOCVD on a patterned GaAs(111) substrate (scale bar: 2µm) and (b) InAs NWs grown hetero-epitaxially by MOCVD on a patterned Si(111) substrate (scale bar: 2µm).

The peculiarity of the approach followed resides in the absence of a catalyst particle as a seed for NW growth, as commonly employed. This avoids the use of certain metals known to be efficient catalysts for NW growth, but killers of Si performance (e.g. Au). Ruling out metal catalysts represents an advantage in view of integration purposes. In-situ observations allow the identification of the growth dynamics switching from a vapor-liquid-solid (VLS) mechanism to a layer-by-layer epitaxy, although the debate on the effective role of the III-precursor is still under investigation. The control of the III-V NW growth direction entails precise constraints: when (111)-oriented substrates are used, growth is achieved accordingly, along the (111) direction. This physical constraint often yields a pronounced 'twinned' structure, whereby crystalline planes are stacked as alternating zincblende and wurtzite segments. The extent of this phenomenon seems to be correlated with the ionicity of the III-V compound. A certain degree of control on the stacking has been achieved only very recently by tuning of the growth parameters. The possibility to precisely control the occurrence of polytypism in III-V NWs could give access to new interesting physics for novel device applications. Theoretical studies showed that periodic twinned superlattices are characterized by a band energy distribution leading to e.g. direct bandgap opening in otherwise indirect semiconductors. Surface and bulk phonon modes are also affected by twinning, leading to new perspectives for thermoelectric applications.

InAs NW growth on non-patterned Si substrates can be achieved by 'engineering' the interaction of specific chemicals (n-decane, toluene) with the pristine Si and Ge surfaces to produce a self-organized pattern. Alternatively, the sole use of an HF pretreament allows to nano-pattern the Si(111) substrate: this option results in non-selective hetero-epitaxy of dense forests of vertical InAs NWs with diameters as low as 20-30nm, see fig. 12. This particular line of research could open new insights into the study of the interaction between III-V materials and group-IV substrates, paving the way to optimized hetero-epitaxy.

Figure 12

Figure 12: (a,b) Tilted and cross-section SEM pictures of InAs NWs grown non-selectively on a HF-pretreated Si(111) substrate (scale bars: 1 and 2µm). (c) A detail of the interface between the InAs NW and the Si(111) substrate is visible by high-resolution transmission electron microscopy (HRTEM) (scale bar: 10nm).

Raman spectroscopy is a valid aid to the investigation of the crystalline and vibrational properties of materials, even down to the nanoscale. In the case of the InAs NW arrays grown, the Raman spectra reveal a distinctive behavior when compared to that of the corresponding InAs bulk. The appearance of surface-optical (SO) modes, and the change in the lineshape of the transverse-optical (TO) and longitudinal-optical (LO) modes are ascribable to the large surface-to-volume ratio, and the onset of quantum confinement and anharmonic effects, respectively fig. 13.

Figure 13

Figure 13: (a) Raman spectra (633 laser excitation) of a bulk InAs(111) substrate compared with that measured on an InAs array grown on Si(111). The longitudinal-optical (LO) and transverse-optical (TO) modes are indicated. (b) Raman spectra of an InAs NW array grown on Si(111) measured at different laser powers. The appearance of a surface-optical (SO) mode is visible between the LO and TO modes.

The NWs are then brought in solution isopropyl alcohol (IPA) and further redispersed onto Si/SiO2 supports. A process flow to identify and contact the NWs via electron-beam lithography was developed, providing extremely flexible and tailorable device design and thus allowing characterization at the single NW level. Electrical characterization of back-gated, single InAs NW FETs suggest the (unintentional) n-type character of the NWs and mobilities in excess of several thousand cm2V-1s-1, see fig. 14.

Figure 14

Figure 14: (a,b) Room-temperature output and transfer characteristics of a back-gated InAs NW FET (inset) contacted by Ni/Au electrodes. The output characteristics are measured at gate voltage Vg=-10, 0, and +10V and the transfer characteristics at drain-source voltage Vds=+1, 5, 11, and 15mV (scale bar: 2µm).

InAs holds a great potential for applications deviating from classical field-effect operation, e.g. spin-based transport or single-electron devices, owing to its large exciton Bohr radius and g-factor when compared to traditional III-V materials (e.g. In1-xGaxAs alloys). InAs is also an ideal test material for studying a class of fundamental phenomena falling in the domain of mesoscopic physics, such as weak localization, and to investigate other aspects of quantum transport in nanostructures (see section Quantum mechanical modeling of the tunnelFET current).

Modeling activities

The impact of a single-gate, double-gate or gate-all-around configuration was finalized, as shown in fig. 15 P18371. The study shows that increased gate control improves the device performance and state-of-the-art body thicknesses below 20nm should be used. However, we also show that the dependence of the TFET performance on body thickness is less strong than the dependence on oxide thickness. Therefore scaling the oxide should remain a key target for TFET optimization C20620, C20957. This year, the impact of stress on the TFET performance has been investigated. In particular, the impact of heterostructure stress in NW-based TFETs is analyzed and shown to be very beneficial. Over two orders of magnitude current increase are predicted, together with an increase of the sub-threshold slope.

Figure 15

Figure 15: Schematic representation of (a) a single-gate, (b) a double-gate and (c) a gate-all-around TFET.

We have also studied the impact of the angle of the source doping region with respect to the gate dielectric. It is shown that the conventional doping shape, which makes a 90 degree angle with respect to the gate dielectric, is typically not optimal. Small angles with respect to the gate dielectric are predicted to improve the current on-off ratio in a given supply voltage window.

Quantum mechanical band-to-band tunneling model development

The current of a TFET is injected into the channel by band-to-band tunneling (BTBT). Currently, all available device simulators have BTBT semi-classically in case of a two-or three-dimensional TFET configuration. We are continuing our effort to develop a full quantum mechanical description of band-to-band tunneling. As a first step, we have finished the analysis of BTBT in a one-dimensional TFET where a non-uniform electric field is applied. The study shows that at the highest electric field, the conventional formula is no longer accurate, and after a first underestimation, the current at very high fields is overestimated P20204, C20460.

Circuit analysis

The TFET will ultimately operate in a larger circuit. The optimization of the TFET configuration should therefore not be restricted to the device optimization, but circuit-based aspects are important as well. This year, we have started a digital-circuit analysis of TFETs, including the short-gate TFET. A transient analysis has been made, the performance of the inverter was investigated and the energy consumption and delay of a three-stage inverter chain was analyzed. The study shows the lack of roadblocks for TFET circuits and highlights the advantages of short-gate TFETs.