Technology-aware design
It can not be underestimated how creative and revolutionary semiconductor scientists and technologists have been in producing chips with ever increasing integration capability, computational capacity, and energy efficiency at decreasing cost per function.
Now that we approach nanometer dimensions, challenges such as energy per operation, leakage power, variability, reliability and degradation finally become real showstoppers. If these challenges can be tackled at all, it will certainly be in an environment such as IMEC, where state-of-the-art expertise coexists that spans the entire semiconductor manufacturing chain, from technology up to system design.
IMEC's technology-aware design (TAD) program`s ambition is bridging the gap between the design community and the technology community, focusing on both analysis and solutions for these scaling challenges.
TAD emphasizes two tracks, one aiming towards analysis (variability aware modeling) (see section Variability-aware modeling) and one to solutions (standardized fine-grained knobs and monitors) (see section Standardized fine-grained knobs and monitors (SKM)).
Variability and reliability aware modeling (VAM) (see section Variability-aware modeling)
During 2007, the largest part of the TAD team's effort was devoted to the creation of the VAM framework. Its goal is enabling a continuous path from technology to system, percolating variability and reliability information over all levels. At the same time it is a central hook to many aspects in variability and reliability research, and a platform to evaluate the effects thereof, see figure 1.
Figure 1: A schematic representation of the projected VAM flow (right), complementing the well known top-down/bottom-up design flow (left). VAM is built on a backbone `information format' at 5 levels of modeling/simulation abstraction. Industry standard tools are used as much as possible to propagate from one level to the other. The lateral arrows indicate where the interaction with the regular design and verification flow happens.
VAM allows anticipating, characterizing and evaluating technology options and their impact on designs and systems in order to evaluate design solutions for scaling issues and to steer technology choices from design decisions. When applied to a real design, exercises of mind, so-called `what if questions' can be answered. Examples of such questions are: how does a certain technology change influence my system yield?, or, which technology option is optimal for my application?
VAM has not the ambition to build new electronic design automation (EDA) simulation tools. It rather builds wrappers and builds on the `information format' (VAM-IF), an ad-hoc standard representation of variability information.
Standardized fine-grained knobs and monitors (SKM) (see section Standardized fine-grained knobs and monitors (SKM))
Variability and reliability are perceived as red brick walls for technology scaling and thus for the entire semiconductor industry. Rather than guaranteeing unreachable variability and reliability specifications at the device technology level, runtime solutions are explored, that engage only when an issue arises during operation.
The design community will have to learn to live with the fact that systems consist of unpredictable and unreliable components. It is not acceptable anymore that a single failing transistor results in a non-yielding system, not at wafer sort time, nor during the application lifetime. Such systems must be able in the field to diagnose and cure (re-adjust, tune, reprogram) themselves, similar to biological systems that can heal themselves. This also helps to fulfill the requirement of absolute fault-tolerance requested in an large number of applications.
IMEC's approach is based on SKMs, as shown in figure 2.
Figure 2: A schematic representation of the SKM principle. Critical circuit parts may be equipped with a monitor and knob circuit. The control algorithm runs in system software, or in firmware or hardware.