ADC solutions
In wireless as well as other applications, the key to achieving high-performance systems is in digital signal processing. But since the world we live in is analog, a critical building block that enables this digital revolution is the analog-to-digital converter (ADC).
Requirements for ADCs vary widely depending on the application. Sampling speeds start from kS/s for e.g. sensor interfaces and go up to GS/s for high-data-rate communications, while the accuracy of the digitization ranges from 4 up to 20bits. IMEC's research advances the current state-of-the-art in ADC results for wireless applications with 3 novel architectures, that each further improves the power efficiency while simultaneously pushing the sampling speed and resolution.
Low-power successive approximation ADC
This year a 9-bit, 50MS/s charge-sharing successive approximation register (SAR) ADC was presented at the 2007 international solid-state circuits conference (ISSCC) with a record-low power-consumption of only 0.7mW C12754. This ADC is targeted to communication standards, such as cellular, wireless local-area network (WLAN), or broadcasting systems, where moderate sampling speeds in combination with high resolution are required.
To reduce the power consumption, a classical architecture such as the SAR ADC has been completely reworked for flexibility and low power. The novel architecture uses passive charge-sharing and an asynchronous controller to reach record minimum power consumption. No active circuits are needed for high-speed operation and all static power is removed, offering a power consumption proportional to sampling frequency from 50MS/s down to 0. The 9bit 50MS/s implementation in 90nm digital CMOS, see figure 1, has a 65fJ/conversion step energy efficiency, which is a factor 2.5x improvement in power efficiency versus the record figure of merit of 2006.
Figure 1: Low-power charge-sharing SAR ADC picture and measurements.
Low-power high-speed Flash ADC
For high bandwidth, high data-rate communication systems such as ultra-wide-band (UWB) and the upcoming 60GHz radio standard (see section 60GHz communications), high-speed (GS/s) low-power moderate resolution (4-6bit) ADCs are required. Typically, these ADCs are implemented with a Flash architecture, although it has an exponential power dependence on the number of bits. Again by modifying the classical Flash architecture, the power consumption has been drastically lowered. The 5-bit 1.75GS/s implementation in 90nm will provide a 25% improvement in power efficiency versus the record figure of merit of 2007.
Low-power medium-speed/resolution ADC
In between the low-speed, higher resolution provided by the SAR ADC and the high-speed lower resolution provided by the Flash ADC, is an architectural gap. By creating a novel ADC architecture that combines the logarithmic power dependency on number of bits of the SAR architecture with the lightweight implementation of a Flash architecture, a power-efficient compromise has been found that indeed provides a performance in terms of sampling speed and resolution situated between the SAR and Flash type ADCs. The 7-bit 150MS/s implementation in 90nm will provide a 6.5x improvement in power efficiency versus the record figure of merit of 2007.