Software-defined radio front-end
Introduction
The demand for the integration of multiple standards into a single portable terminal is growing together with the proliferation of wireless communication standards. Such handsets could be implemented with multiple dedicated front-ends integrated in parallel. However, this solution is far from optimal for cost. A software-defined radio (SDR) transceiver optimizes the functionality versus area trade-off, by programming a versatile front-end to the desired standard. The boundary conditions being that for each supported standard both performance and power consumption should be comparable to dedicated solutions.
The research focuses on the development of key technologies to enable transceiver designs that handle radio-frequency (RF) signals from several applications and standards, among which for example third and fourth generation cellular (3G-4G), such as universal mobile telecommunication standard (UMTS), 802.16e and 3rd generation partnership project-long term evolution (3GPP-LTE) (see section Software-defined radio baseband), but also wireless local-area network standards (WLAN 802.11a,b,g,j & .11n), wireless personal-area networks (802.15.1,4), broadcasting standards such as digital video broadcast (DVB), digital audio broadcast (DAB), etc.
Main achievements in 2007
In 2007, IMEC realized world's first prototype of a true SDR transceiver IC which can be widely programmed to operate with all present and future standards in the frequency range between 174MHz and 6GHz C12753, C14404. The reconfigurable radio front-end IC in 130nm technology uses only 1.2V supply voltage and has an active area of 7.7mm2. Depending on its configuration the SDR front-end has a power consumption ranging from 60 to 120mA which is comparable to state-of-the-art single-mode radios. Its architecture is presented in figure 1. Figure 2 shows a microphotograph of the SDR front-end with highlights on the major circuits.
Figure 1: Block-diagram of the implemented software-defined radio transceiver.
Figure 2: SDR chip microphotograph.
The SDR transceiver front-end includes a fully reconfigurable direct-conversion receiver, transmitter and two synthesizers for frequency division duplex (FDD) mode. The synthesizers can generate I/Q local-oscillator signals for frequencies ranging from 174MHz up to 6GHz based on a single, extreme wideband and power-efficient voltage-controlled oscillator (VCO) P14171. Another key building block is the ultra-flexible baseband analog low-pass filter with a programmable cut-off frequency between 0.35MHz and 23.5MHz. Besides its bandwidth also the noise level and selectivity can be conveniently modified, depending on the environmental conditions, leading to a further power saving P12940. The performance of the filter as well as all other blocks can be digitally adjusted over a wide range of specifications through a novel type of analog network on chip. Using these different configuration `knobs', the overall front-end performance (RF carrier frequency, channel bandwidth, noise figure, linearity, filter characteristic, etc.) and power can be tuned to the specific requirements of the different standards to be covered. Moreover, there is an equally important perspective of energy optimization. Using the same reconfiguration knobs, the front-end can significantly reduce its power consumption by exploiting real-time power/performance trade-off opportunities when allowed by the conditions of the environment, e.g. by reducing the filtering level when the interferer level is lower than the worst case defined by the standard. For this energy optimization a close interaction between two competence fields is required: IC design on the one hand and cross-layer modeling and optimization (see section Cross-layer (Quality of Experience)) on the other hand.
New mixed-signal control, calibration and compensation techniques PA21 are used to relax the specifications in the analog domain and hence to lower the cost and risk of analog circuit design.
Future research
In the coming years the research will focus on novel SDR front-end architectures that are optimized for digital system-on-chip technologies and that reduce as well the surface acoustic wave (SAW) filtering requirements, reducing the cost of such systems. This will build on results coming from ADC research (see section ADC solutions) as well as research on circuits for deeply scaled CMOS (see section Analog and RF ICs for CMOS generations beyond 45 nm).