APOLLO research strategy
The digitalization of electronics enables the convergence of high quality multi-media services with high speed data communication. As such this offers ubiquitous access to the Internet and anywhere, anytime usage of services, content and applications on any network. The consumer should be able to access services and information at home, walking in urban areas, driving his car, driving to work and even in more desolated areas. As such, mobile terminals will have to efficiently deal with a multitude of communication modes (such as wireless local-area network advanced video coding (WLAN), 3G/4G, 802.16e and digital video broadcast for handhelds (DVB-H)) and content formats (such as moving picture expert group (MPEG)-2, MPEG-4, AVC/H.264 and scalable video coding(SVC)).
The APOLLO research program is focused on the development of technologies for the future multi-mode multimedia terminal, i.e., a terminal that enables ubiquitous mobile communication. It requires that various communication modes need to be supported, leading to the concepts of software defined radio (SDR) and cognitive radio. The required flexibility and high performance lead to heterogeneous multiprocessor platforms. The enabling technologies to realize these platforms and to efficiently map on them are advanced compiler technology, multiprocessor mapping technology and reliable system design techniques in sub-45nm CMOS technologies. The research program targets both the front-end as well as the baseband part of the communications engine. In addition, it applies the enabling technologies to arrive at efficient multimedia implementations. Finally, since power consumption is critical in mobile devices, cross-layer optimization techniques are being developed to minimize power across all layers of the terminal depending on actual environmental conditions and user requirements.
The basic research focuses on topics for products with a market introduction before 2012, while the more exploratory research, identified as long term (LTR) research focuses on topics with a product horizon that goes beyond 2012.
Architecture and compiler technology (ACT)
The challenge addressed by ACT is to provide multi-mode multimedia terminals with flexible hardware platforms that meet at the same time low-power constraints and achieve high-performance targets. The complex applications to be executed on such platforms can be partitioned in multiple parts, each of which has different performance/power and flexibility requirements. To balance the required performance of each part with the available power budget for that part, heterogeneous multiprocessor systems are employed. The architecture and compiler research program focuses on processors architecture for dynamically reconfigurable embedded systems (ADRES) and on the compilers dynamically reconfigurable embedded system compiler (DRESC) to generate code for those processors. IMEC's general vision on processors that run all but the smallest application parts acknowledges that processor features that are not supported by compilers are of very little use, given the complexity of the programs to be compiled and the short time-to-market requirements of the applications. By consequence, processors should not only offer high performance at low power consumption, but they should also provide the flexibility required for automated compilation starting from high-level programming languages like C. Moreover, given the need to run multiple application types on devices, such as video codecs, 3D rendering algorithms, and wireless communication algorithms, the processors should offer enough flexibility to execute such a wide range of application types efficiently (see section Power-efficient compiler technology and processor architectures).
Multi-processor system-on-chip (MPSoC)
To meet the high-performance targets for multi-mode multimedia terminals while keeping the expected flexibility, MPSoC platforms are required. In recent years, various MPSoC platforms have been introduced by the industry. However, a significant gap remains with respect to application mapping tools and with respect to runtime management of the current and the future, more advanced, MPSoC platforms.
The overall goal of the MPSoC research activity is to develop tools that allow to achieve a decreased average time-to-market, with a lower risk (both in time and in performance) when mapping (delivering) and integrating software application components and hardware/software services on top of an MPSoC platform (see section Multi-processor system-on-chip (MPSoC)).
Technology-aware design (TAD)
Advanced process technology is required to meet the high performance and low-power requirements for the components of a multi-mode multimedia terminal. However, advanced sub-45nm process technologies suffer from increasing process variability. This clearly degrades the actual performance of the manufactured overall system, unless larger design margins are taken for the individual blocks in the design to accommodate the worst case delay. This, however, leads to designs that are more expensive in terms of area and power. Clearly, this effect becomes more prominent in blocks with very tight latency constraints (e.g., processors, small memories and busses) where not only more power is being consumed but also the gap between the performance required by the system and the one offered by the manufactured memory becomes larger at every technology node. Moreover, due to variability in combination with progressive degradation of electrical parameters of devices and interconnects (due to new deep submicron reliability phenomena), the system experiences both of the effects as a global time-dependent variability problem. Analysis and solution techniques generic enough to tackle such combined problem are completely missing in today's state-of-the-art.
The goal of the TAD program is offering design solutions to sub-45nm scaling issues and is broken down in (1) modeling the imperfection and (2) designing with unreliable and irreproducible circuit parts (see section Technology-aware design (TAD)).
SDR-baseband (BB)
Future wireless systems of the fourth generation (4G) aim to support a wide variety of services over a wide variety of networks in a way transparent to the user. SDR terminals are crucial to enable seamless and transparent inter-working between these different wireless access systems or communication modes. On the longer term, SDRs will be extended to become cognitive radios coupling energy savings to efficient spectrum usage.
The SDR `flexible air interface' (FLAI) project targets to deliver SDR baseband solutions for nomadic terminals, with a cost- and power-efficient integrated architecture supporting all radio standards from code-division multiple access (CDMA) third generation partnership program long-term evolution (3GPP-LTE) up-to the most demanding orthogonal frequency division multiplexing (OFDM)-based communication standards (802.11n, 802.16e, DVB-H). This goal is achieved with a heterogeneous MPSoC platform for the baseband processing, and algorithmic solutions to bring standards real-life wireless, incl. synchronization and analog front-end non-ideality compensation (crystal frequency offset, IQ imbalance, phase noise) techniques to achieve a high spectral efficiency at low cost and power. Scalability is provided in the architecture and algorithms to enable trading off performance and power.
Furthermore, the growing demand for large data rates reveals an increasing spectrum scarcity. New paradigms for efficiently exploiting the spectrum are clearly needed in this context. A continuously growing role for smart/adaptive spectrum-agile radios exploiting the capabilities of reconfigurable radio architectures is to be expected. Pushed to the limit, this leads to the disruptive concept of cognitive radio (CR). Such a CR is defined as a radio that can autonomously change its transmission parameters based on interaction with the complex environment (radio scene, application and user requirements) in which it operates. The `fully flexible' cognitive radio is investigated in the LTR (see section Software-defined radio baseband).
SDR-front end (FE)
A software-defined, multi-mode radio is a radio that can serve multiple standards, with several modes of operation within each of these standards (e.g. time division duplex or frequency division duplex, constellation size, coding rate). The radio implementation is flexible to provide a dedicated hardware configuration for each of the standards considered, which can be extended to the different modes in these standards.
In this research, focus is on digital radio transceivers to enable Gbit/s cognitive radios for wireless terminals. It is of enormous importance for the successful commercial deployment of these Gbit/s communications that efficient techniques are developed to implement RF transceivers in deeply scaled digital-only CMOS technologies; no analog options are allowed.
The research focuses on the development of key technologies to enable transceiver designs that handle RF signals from several applications and standards, among which for example 3G-4G, such as universal mobile telecommunication standard (UMTS), 802.16e and 3GPP-LTE, but also WLAN standards (WLAN 802.11a,b,g,j & .11n), wireless personal area networks (WLAN 802.15.1,4) and broadcasting standards such as digital video broadcast (DVB), digital audio broadcast (DAB), etc. (see section Software-defined radio front-end).
ADC solutions
In wireless as well as other applications, the key to achieve high-performance systems is in digital signal processing. But since the world we live in is analog, the key building block that enables this digital revolution is the analog-to-digital converter (ADC). Requirements for ADCs vary widely depending on the application. Sampling speeds start from kS/s for e.g. sensor interfaces and go up to GS/s for high-data-rate communications, while the accuracy of the digitization ranges from 4 up to 20bits. IMEC's research advances the current state-of-the-art in ADC results for wireless applications (see section ADC solutions).
Analog and RF circuits in 45nm CMOS and beyond (LTR)
CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. A multi-gate device such as a FinFET is such a new architecture. IMEC has evaluated the different device options, both in planar bulk CMOS and in FinFET technology, on their potential for analog and RF applications. The part of the program described in this section focuses on analog and RF design. From measurements on functional circuits (see below) and circuit simulations it is found that FinFET-based circuits for low to moderate speed, low-power applications outperform comparable realizations in planar bulk CMOS. In the microwave and millimeter-wave frequency region planar bulk CMOS is still superior (see section RF-CMOS front-ends).
60GHz communications (LTR)
The demand for wireless connectivity is ever increasing. Short-range wireless links will soon be expected to deliver bit rates of over 1Gbps to keep on satisfying this demand. As the frequency spectrum below 10GHz is getting completely congested, bandwidth for Gbps links has to be found at higher frequencies. In most countries, several GHz of bandwidth is now available in the 60GHz band for this kind of applications.
The goal of this research is the development of different parts for a 60GHz WPAN communication system that can handle bit rates above 2 Gigabit per second. An air interface will be developed that enables this high bit rate, and that allows for a cheap implementation of the radio part including the antenna. This radio part, which will also be developed in this project, will be realized as a CMOS IC. This IC will be combined with the different antennas into one single module (system-in-a-Package). Thin-film passive integration technology and advanced packaging technologies will be used for the realization of the antenna and antenna interface (see section 60GHz communications).
Multimedia
Within the APOLLO research program, the multimedia research focuses on driving and proving the MPSoC design flow and tools. Multimedia applications require a very high performance which can only be realized by using the combined computational horsepower of multiple processors. Starting from reference code for multimedia standards (typically C or C++ code), the challenge for the multimedia application programmer is to distribute the application over the available processors, while balancing the load on the different processors and managing the load on the communication and memory infrastructure, to meet the power budget (see section 3D visual systems).
Cross-layer optimization (XL)
To make energy-efficient reconfigurable terminals a reality, cross-layer (XL) control algorithms are targeted for multimedia wireless communication systems. The goal is to minimize the total energy consumption in the system, while providing the just required performance expected by the user. A two-step approach is advocated to do so. First, energy scalability is enabled in the design of the reconfigurable radio terminal. Secondly, this scalability is exploited at run-time to achieve low power operation, by following the dynamics in the application requirements and propagation conditions, through XL joint quality of service (QoS) and energy management.
To validate the approach and characterize the associated energy gains, it was instantiated in use cases, which can be regarded as proof-of-concept studies, showing the applicability of the proposed system-level (XL) management framework in practical systems. The scope of the considered use cases is on multimedia content transmission over wireless access networks (i.e., over the connection(s) between an access point/base station and the wireless terminal device(s)). Terminal-driven control solutions are targeted in all considered use cases. Additional benefits of the involvement of the access point/base station will in some cases also be investigated (see section Cross-layer (Quality of Experience)).