Next-generation flip-chip and substrate technology
This year, IMEC has defined a new research program in partnership with the packaging research center at Georgia tech (GT-PRC)-Atlanta, to explore, develop and demonstrate a total UBM interconnection, underfill and substrate solution for flip-chip packaging of next-generation fine pitch ultra-low-k/Cu and other devices. The objectives of the proposed research are to demonstrate next-generation flip-chip technologies at 20-50micron interconnection pitch with organic substrates that support high frequency analog and high speed digital applications at high power. The semiconductor industry sees four major barriers to continue the trend towards scaled ICs and ultra-low-k dielectric ICs with flip-chip scaling:
- The package interposer substrate: package downscaling to fine pitch below 50 microns is limited by substrate warpage which is governed by modulus of the core, and CTE mismatch between silicon and the substrate.
- Fine pitch flip-chip increases the thermo-mechanical stress and strain of the solder joints. Thermal cycling reliability may be reduced with a factor Ø3. Processing flip-chip interconnections at fine pitch is also limited by the current technology limitations of solder plating, printing and assembly and alignment tools.
- Electro-migration (EM): Scaling down Interconnect geometries results in a quadratic current density increase. Low melting point and high diffusivity solder materials are not electro-migration resistant to meet future current density and geometry requirements.
- Thermo-mechanical reliability of ultra-low-k ICs: flip-chip packaging to fragile low-k dielectric ICs aggravates the stress-strain concerns, requiring a fundamentally-different system-approach from the ultra-low k die, UBM, interconnections, interfaces, and the substrate. The convergence of nano-micro-macro scale structures and heterogeneous materials require a new set of predictive modeling design and characterization tools.
The consortium proposes to go beyond traditional flip-chip interconnections by providing a total system-level solution based on novel concepts in:
- Electrical modeling, design and characterization;
- Advanced interconnection and assembly materials and processes with novel UBM/barriers and underfills;
- Advanced multilayer and fine pitch organic substrates with stress relief approaches and
- Thermo-mechanical modeling and design for low-stress interconnections;
- The final goal of this two-year research program is to demonstrate;
- Thermomechanical reliability at 20 micron (peripheral)-50 micron (area array) pitch;
- Electro-migration resistance with flip-chip scaling and
- High electrical performance to meet the high-speed signal and high-power density requirements.