3D-WLP: micro-bumping
The continuous downscaling of IC dimensions puts constraints on solder flip-chip bumps. Simultaneously with bond-pad diameter scaling, also the bump height scales accordingly. Since the intermetallic compound (IMC), which is formed at the interface between metallization finish and solder, remains constant in thickness, the relative amount of remaining ductile solder material reduces with downscaling. This will eventually lead to joints which fully consist of intermetallics only.
It compromises the mechanical performance of the flip-chip interconnection since the intermetallic phases are known to be brittle. On the other hand, because of the higher melting point of the formed intermetallic phases compared to the parenting solder layer, the thermal performance of such an interconnection is outstanding. This makes intermetallic micro-bumps highly suitable for 3D-stacking.
Micro-bump metallization systems
All combinations of solderable metallization layers and solder alloys can be used for the formation of intermetallic micro-bumps. Currently Cu-Sn figure, see figure 1 and Co-Sn figure 2 micro-bumps are under investigation. Cu is a well-known and frequently used metallization finish which forms two intermetallic phases with Sn: Cu3Sn and Cu6Sn5; Co (see EP1732116A and US 2006/0292824A) is used because of the fast formation of a single intermetallic phase (CoSn2) which is believed to have beneficial mechanical properties. The formation of a single intermetallic phase enhances the stability of the joint as will be shown in the following section.
Figure 1: Enlarged view of a Cu-Sn micro-bump cross-section showing a 2-phase intermetallic interconnection.
Figure 2: Cross-section of a 20µm diameter Co-Sn micro-bump showing a single phase intermetallic interconnection.
Figure 3: Typical resistance measurements of 20m diameter Cu-Sn and Co-Sn single IMC micro-bumps which are stressed with an electrical current of 200mA at 150oC.
Thermal and electrical performance
Due to the higher melting point, the final operating temperature of these intermetallic interconnections may be higher than the joint's processing temperature which is the melting point of the solder. They are therefore most suitable for high-temperature applications or 3D-stacked devices. In this latter case, there is no risk for re-melting first-level interconnections during subsequent bonding steps of stacking devices on top of each other. Furthermore, for similar operating conditions, interdiffusion and from that electro-migration is expected to be lower in intermetallic interconnections compared to standard solder flip-chip bumps.
For small diameter interconnections, electromigration failures are expected to increase because of higher current density values. For intermetallic micro-bumps however, experiments show that when they are subjected to electromigration test conditions which are 10 times larger in terms of current density (0.63mA/µm2) compared to electromigration triggering values for standard solder interconnections (0.05mA/µm2), no failures or electromigration damage is observed after more than 1000h of testing at 150oC. A typical resistance measurement of a current-stressed Cu-Sn and Co-Sn single joint is shown below, see figure 3. No resistance change is observed for the Co-Sn IMC bumps while a resistance decrease to a plateau value is observed for the Cu-Sn IMC bumps. This behavior can be correlated to the evolution of the microstructure. No microstructural change is observed for the single phase Co-Sn IMC joints while the initially 2-phase containing Cu-Sn IMC micro-bump (with both Cu3Sn and Cu6Sn5 present) has transformed into the expected final equilibrium state of a single phase with the highest Cu containing IMC stoichiometry (Cu3Sn) only. The resistance reduction can be attributed to the respective resistivity values for the different intermetallic phases (ρ=17.5µΩcm for Cu6Sn5 and ρ=8.8µΩcm for Cu3Sn).
These results indicate that intermetallic micro-bumps are highly stable under thermal and electrical loads which make them suitable for advanced fine pitch interconnections.