Multilayer-thin-film
The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called “interconnect technology gap”. Multilayer-thin-film technology is proposed as a “bridge”-technology between the very high density IC technology and the coarse standard PCB technology. The key features of a multilayer-thin-film technology are the use of wafer-like low-temperature process steps and the use of low cost thin-film lithography.
The basic elements of such an interconnect technology are a thin-film high-density metallization technology and a thin-film, dielectric deposition technique. With the recent needs for further miniaturization and heterogeneous integration, the technology can be associated to bulk micro-machining to realize 3D interconnects (see section 3D WLP (through-silicon via technology)). The preferred interconnect metallization is based on semi-additive electroplating of copper. The minimal line width and line spacing for such lines go down to 5 µm for 5 µm thick metal tracks. The preferred dielectric layers are spin-on or spray-on photosensitive polymer layers, enabling high density via connections between the interconnect layers (>400 /mm2).
In addition to the interconnect function, thin-film technology can also be adequately used to integrated various passive components, such as resistors, capacitors and inductors. This technology enables the realization of true “system-in-a-package” (SiP) solutions, combining multiple “system-on-a-chip” (SOC) IC's with other components and also integrating passive components in its layers.
Figure 1: Photograph of thin-film realization (RF module with landing pads for 3D TSV feedtrough).
The thin-film technology platform can be use in various fields of the “More than Moore” world. As the technology can be used to build interconnects and/or wafer level redistribution, it shows also high added value for integrated passives.. This year the capacitive RF-MEMS technology was developed in a multi-layer thin-film fashion, the process were robust enough on 200mm to enable the use of the switches for (see figure 2). Besides the addition of RF functions in the package, the technology enables the use of wearable and stretchable electronics , also (see section Strategy).
Figure 2: SEM Photograph of capacitive RF MEMS.
Figure 3: Photograph of bio-implantable device (active dies embedded in a silicone matrix).