BiCMOS technology
The further improvements of the performance of SiGe:C heterojunction biopolar transistors (HBTs) in the 0.13µm BiCMOS process proceeded along two paths. The first path is the evolutionary scaling of a quasi self-aligned (QSA) architecture, with the introduction of airgap deep-trench isolation (DTI), collector cavities under the external base regions, and Ge-spiked mono-emitters. The second path is based on a disruptive change in architecture, with the invention, and process optimization of a novel self-aligned emitter/base/collector architecture, which has the potential of very low parasitics.
Evolutionary scaling of the quasi self-aligned SiGeC HBT
To reduce the peripheral collector/substrate capacitance, a novel DTI was demonstrated for the first time in the 0.13µm BiCMOS process flow in 2006. The airgap DTI does not require additional masking steps, and is fully compatible with the standard shallow trench isolation. Figure 1 shows a scanning electron microscopy (SEM) cross-section of the SiGe:C HBT with the airgap DTI. The resulting reduction of the collector/substrate capacitance improved the fmax to 275GHz for an fT of 205GHz, and state-of-the-art BiCMOS current mode logic (CML) gate delays of 3.5ps were obtained. The BVceo breakdown voltage was 1.85V. Further optimization of the process steps resulted in a larger process window for the deep trench etch, and in better planarization. The airgap DTI is now standard in the 0.13µm BiCMOS flow.
Figure 1: Airgap deep-trench isolation.
Oxide filled cavities were used to decouple the external base region from the collector region. This was accomplished by incorporating a 15nm thick Si0.75Ge0.25 layer in the epitaxial collector region. After STI etch, a CF4-based etch step laterally undercuts the external base regions. After sidewall oxidation and shallow trench fill, the cavities are almost completely filled with oxide.
The resulting device performance improvement is from a fT/fmax combination of 205/275GHz to 210/290GHz. The novel isolation scheme was demonstrated in full 0.13µm BiCMOS integration lots, with no significant impact on the CMOS device characteristics.
SiGe:C HBTs typically have quite a high current gain. This high current gain reduces the breakdown voltage between emitter and collector (with the base open). Using a Ge spike in the emitter increases the base current. When this Ge spike is integrated by replacing the poly-emitter module by a Ge-spiked mono-emitter module, the breakdown voltage is improved without sacrificing on the cutoff frequency.
Novel device architecture
First results were obtained for a novel fully self-aligned SiGe:C HBT which features a single-step epitaxial collector/base process.
This architecture allows for a strong reduction of the device parasitics. The collector drift region and the extrinsic base are made self-aligned to the emitter by means of a dry etch that removes all polycrystalline material. The remaining epitaxial pedestal defines the intrinsic device and makes DTI redundant. The first fabricated devices showed a fT/fmax of 300/220GHz. A SEM cross-section is shown in figure 2.
Figure 2: Novel fully self-aligned HBT architecture.
A new mask set was taped out, with scaled layout rules. Dummies were added to facilitate the chemical-mechanical polishing (CMP) processes needed for the reconstruction of the external base contacts, after the pedestal etch.