Strategy of Ge/III-V program

Since 2005, the strategy of this program pursues a combination of Ge pMOS with III-V nMOS. In the Ge MOS devices research program further improvement of the short-channel pMOS could be demonstrated (see section Ge MOS devices). In the III-V MOS device research program a major improvement of the interpretation of CV curves to measure Fermi-level pinning was obtained (see section III-V MOS devices).

Both programs contribute to the strategy of the Ge/III-V program. Details of the research are published in C15160, C15093, P14717, P14862, C14866, C14867, P14868, P15479, C15528, P14363, C14829, C14915, P14931, C14657, C14876, P13605, C14544, P15415, P15334, C14420, C14715, P14798, C14813, P14362, P15112, P15159, C15161, C15162, P15338, P14513, C14881, P14617, P14619, P14621, P14926, C14923, C15118, C14510, P15110, P12954, C14566, C14567, P14359, P14360, P14361, C14628, P14726, P14800, C14872, C14913, C15689, C15416, P14719, P14795, P14930, PN36, PA7, PA69.

To allow the combination of Ge pMOS with III-V nMOS devices, the passivation of the gate stack will be a key element. For this purpose a molecular-beam epitaxy (MBE) cluster tool was installed in the IMEC clean room facilities (see figure 1. This cluster tool combines a III-V MBE growth chamber (for growing GaAs and InGaAs layers on Ge), a cleaning chamber for preparation of the interfacial layers and a high-k molecular-beam deposition growth chamber (for growing interfacial layers, high-k dielectrics and in-situ metal gates). It can process 2”, 100mm and 200mm wafers. Acceptance tests of the tool were successfully finalized in 2007. This tool enables a perfect in-situ control of each interface of the channel and the gate stack materials.

Figure 1

Figure 1: The MBE cluster tool for growing in-situ III-V layers, interfacial layers, high-k dielectric layers and metal gates with perfect ambient control.

top