Floating-gate devices
Still, the floating-gate concept is dominating the non-volatile memory business. Therefore, all possible routes to push the corresponding roadmap have to be seriously investigated. The main challenges here are the further planarization of the cell which induces a loss of coupling ratio (for stand-alone memory), and the lack of voltage scaling (embedded memories). Therefore, the program focuses on the implementation of high-k interpoly dielectrics in order to enhance the coupling and/or reduce the operating voltage. The main challenge is not to compromise the retention specifications. Also engineered barriers for tunnel oxide replacement are being explored for controlling the disturb margins in NAND Flash arrays as well as for retention improvement. In this case, the main challenge is to obtain sufficient write/erase endurance. A large effort is now dedicated to trap characterization using electrical techniques which serves as an input for the refinement of the leakage models used to predict retention in these advanced memory cells P14099.
Interpoly dielectric (IPD)
The work on IPDs has been continued along 3 major lines. First, the AlO-based solution has been optimized and a winner stack has been found which guarantees 10 years of retention before and after cycling. Moreover, the stack uses only a 1-nm thin interfacial oxide between the floating gate and the high-k material which allows to obtain EOT values of ~6nm. This offers a good solution for embedded memories (which will continue to use the sidewall coupling component) as well as for planarized T-shaped cells which offer an intermediate solution for stand-alone technology C14215, PA34. Secondly, the work on ZrAlO has been discontinued because no workable stack was found in the full parameter space. For HfAlO the jury is still out and last experiments are running to find a higher-k IPD based on this material for fully planar stand-alone memory technology C14216, PA88, PA93.
Figure 1: Intrinsic retention characteristics for different AlO-based IPD stacks at elevated temperatures
Finally, also more exotic materials have been explored such as DyScO, DyO, HfLaO. While the latter two show some flaws from first experiments, the DyScO case is promising since it provides a very large programming window combined with good retention even at elevated temperature. Further investigation is needed to confirm and explain these findings. Other Hf-based materials such as HfSiON and HfO2 are ruled out from further research because of too high leakage levels which are caused by a high density of shallow traps.
More basic insight in leakage currents through such stacks has been obtained by the optimization of charge pumping and pulsed CV measurements for the in-depth analysis of the trap properties. Based on a mathematical model for the trapping of electrons in the high-k layer, the charge-pumping signal could be modeled which allows to extract the trap density contours in the layer as a function of energy and distance from the interface. A first comparison with the trap-assisted tunneling model shows excellent agreement for the case of AlO-based layers.
Tunnel barrier engineering
In order to reduce program/erase voltages, IMEC investigates engineered tunneling barriers of the variable oxide thickness (VARIOT)-type. Such voltage reduction has been demonstrated already however at the expense of endurance (AlO-based layers) or retention (Hf-based layers). Apart from the leakage issue see previous section on Interpoly dielectric (IPD), such a solution also requires that the charge trapping is minimized which is found to be possible with HfSiON layers. In that case, however, top oxide integrity is crucial to preserve retention. Secondly, the VARIOT stack can also be used to increase disturb margins in NAND arrays provided that trap-assisted-tunneling is negligible under disturb conditions. Finally, the VARIOT principle can also be applied to TANOS-type cells (see section Nitride-based technology) without the need for a top oxide C14541. In the latter case, the engineered barrier concept imposes even more constraints on the material parameters because it has to work both for electrons (conduction band) as well as for holes (valence band).
Figure 2: Band diagram of the VARIOT' engineered barrier under programming and disturb conditions, respectively.