3D wafer-level packaging (3D-WLP)
Introduction
3D technologies hold the promise to further enable system performance increase in a time where device scaling has become increasingly challenging. However, 3D technologies will need to be tailored to the needs of the application they will serve. IMEC's 3D program addresses key challenges on the road to realizing 3D integrated systems. It consists of three tightly coupled subprograms: 3D-SIC (see section 3D-SIC: stacked ICs), and 3D-WLP, (see section 3D-WLP: micro-bumping), both tackling the process technology challenges and 3D-SOC Design (see section 3D Design), focusing on the design challenges.
IMEC's 3D-WLP technology platform uses wafer-level-packaging technology in combination with deep reactive ion etching (DRIE) to fabricate 3D interconnects. These now directly interconnect one die with another without routing via the package and are true zero-level packaging interconnects. The technology targets application in the production of heterogeneously integrated systems and memory stacks. IMEC's 3D-WLP technology platform uses wafer-level-packaging technology in combination with deep reactive ion etching (DRIE) to fabricate 3D interconnects. These now directly interconnect one die with another without routing via the package and are true zero-level packaging interconnects. The technology targets application in the production of heterogeneously integrated systems and memory stacks.
3D-WLP Processing: Phase I Through-SI vias
Using the 3D-WLP technology platform we demonstrated through-Si via chains. First 200mm standard silicon wafers with a patterned aluminum layer on the front where glued face down to a glass carrier and thinned down to a final thickness of 100μm using a conventional grinding process. After a particle clean, sloped vias are etched from the back side of the wafer connecting to the metal traces on the front side of the thinned wafer. Next a conformal 1-2μm thick Parylene N layer is deposited by chemical vapor deposition. The Parylene layer is opened at the bottom of the vias in order for the via to electrically connect to the Al pads at the front side of the wafer. Subsequently the via is metalized using a semi additive deposition process based on similar to the on used in redistribution technology. The test vehicle carried through-Si vias with diverse diameters. A top view SEM picture of such a via is shown in figure 1 whereas figure 2 shows a SEM image after FIB cross section.
Figure 1: Top view SEM picture of a 3D-WLP phase I via after conformal via metallization.
Figure 2: SEM picture after FIB cross sectioning of a conformally metalized 3D-WLP phase I via.
Phase I Via chain characterization
I-V curves of various daisy chains corresponding to three different dimensions of vias are measured. Each of these measurements is then divided by the number of vias in the corresponding daisy chain to get resistance per daisy chain element. Figure 3 plots the results of these measurements, where each dot in the graph corresponds to a different daisy chain. This graph shows that the resistance of a daisy chain element increases while the size of the via reduces. Since the pitch of the daisy chain element is constant, this increase is mainly due to the metal interconnect lines, i.e., as the via gets smaller the metal connection lines get longer.
Figure 3: Resistance per daisy chain element measurement results for three different via dimensions. Each dot in the graph corresponds to a different chain. The trend in the graph is mainly due to metal interconnect line which are getting longer as the via gets smaller since the via pitch is constant.
Through-Si via scaling: Phase II Through-SI vias
Despite the above described encouraging electrical results, the scaling the vias made using the phase I flow is very challenging: for narrow vias, limitations of the 1X proximity litho process prevents opening the polymer isolation at the bottom of the via with a high yield. An alternative process flow that avoids the necessity of patterning at the bottom of a deep via has been proposed. The new flow involves etching a ring-shaped trench and filling it with a spin-on polymer first. In a second step the center Si piece, enclosed in the Si-ring trench is etched away. This process leaves a thick polymer isolation layer on the via sidewall that is naturally open at the via bottom. Figure 4 shows a cross section SEM picture of a sea of Phase II vias after partial trench fill using a spin-on dielectric: the dielectric penetrates to the bottom of the trench and fills the trench bottom without leaving voids inside the dielectric.
Figure 4: Cross section SEM picture of a sea of Phase II vias after partial trench fill using a spin-on dielectric.