Cu/low-k interconnects
The Cu/low-k and the 3D stacked IC program form the advanced interconnects program. Whereas the Cu/low-k program investigates the materials, process and reliability aspects of scaled interconnects, the 3D stacked IC program (see section 3D-SIC: stacked ICs) looks into the staking of integrated circuits by means of high density vias and Cu-to-Cu bonding.
In 2007, the Cu/low-k program focused on the following topics:
- pitch and CD scaling of damascene structures for the 22 and 32nm technology nodes;
- scaling of the dielectric constant;
- barrier and dielectric reliability (see section Low-k dielectric reliability);
- advanced barrier, Cu seed, Cu resistivity and Cu contacts;
- electromigration of narrow wires (see section Electromigration and stress-induced voiding).
More information on the strategy of the Advanced Interconnect program can be found in Strategy of Interconnects IIAP (see section Strategy)SR001
.
Pitch and CD scaling of damascene structures for the 22 and 32nm technology nodes
At the SPIE 2007 advanced lithography symposium, double patterning with 193nm immersion lithography emerged as one of the most viable patterning options that will take the industry to the 32nm technology node and beyond. The Cu/low-k program presented an approach for 50nm half-pitch interconnects, using a litho-etch-litho-etch approach on metal hard mask C12958. Since a 0.85NA immersion scanner is used, the small pitch of 100nm is obtained by double patterning; the small trenches are made by quasar exposure followed by a shrink technique, in which a layer is coated over the resist patterns. This results in a reduction of the spacing between the resist lines, such that the target of 50nm for the trenches can be met. For mask making, a design split is carried out, followed by adjustments of the basic design to make the patterns more litho-friendly. Assist features are placed next to isolated trenches to ensure sufficient depth of focus. Furthermore, an adjusted optical proximity correction is carried out, taking into account proximity effects of both the exposure and the subsequent shrink process. This patterning process was applied to a porous low-k dielectric with k=2.5. Particular attention was paid to the overlay of printA towards printB, profile and critical dimension (CD) control during etch, wet clean after double-patterning and chemical mechanical polishing (CMP) of the overburden to realize yielding structures. A yield of the order of 90% was obtained on meander-fork structures. The sensitivity of the double patterning process towards overlay errors was checked electrically by means of shifted meander-fork structures. It was found that the overlay accuracy has to be controlled to values below 10nm to avoid yield loss C15354.
Figure 1: Schematic of the double-patterning sequence used for 50nm half pitch Cu/low-k damascene single-damascene structure.
Figure 2: 100nm pitch meander fork structures created in low-k with k=2.5 with double patterning. Right: distribution of the sheet resistance. Left: scanning transmission electron microscopy (STEM) micrograph of the single-damascene structures (dark field).
Semiconductor production is expected to soon reach the lower limit on feature dimensions achievable with current dry or even high-NA immersion-based 193nm lithography, particularly for contacts/vias and trenches. Several techniques for post-exposure shrinking of printed features have been proposed, but the shrink that can be obtained is in most cases limited to about 20nm. An alternative shrink method has been explored, in which a plasma-generated polymer coating is deposited on the top and sidewalls of the lithographically-defined patterns, reducing the critical dimensions C14527. The amount of reduction of critical dimension can be controlled through the number of shrink process cycles applied. Typical examples of CD shrink on contact patterns are shown in figure 3. For this study, varying shrink processes were applied to contact and trench structures, which were then evaluated for CD reduction, integration capability, and electrical performance. As the shrink of the critical dimensions becomes an integral part of the patterning process, optical proximity correction models need to take into account the specifics of the shrink process C12977.
Figure 3: Representative contact CD results (post- etch/ash), using a plasma assisted shrink process. The amount of CD reduction increases with increasing numbers of shrink process cycles.
The Cu/low-k program aims at generating early learning on the filling and the resistivity of narrow Cu wires, which cannot be printed by optical lithography today. There are several references in the literature which use either backfilled tetraethyl orthosilicate (TEOS) trench liners or a shrink based process to generate sub-lithographic structures. The narrowest backfilled structures generally yield very sloped trench entrant profiles which make filling much simpler than for more realistic rectangular cross sections. The shrink processes based on coating a layer on top of the resist lines generally have a maximum width reduction of about 30nm with associated increases in sidewall roughness and yield fallout. A novel process based on the sacrificial removal of a Si fin was chosen C15349. This process flow leverages the sub-lithographic processing used for FINFET transistors. An overview of this process flow is shown in figure 4. In particular the FiNFET process uses a very uniform and controlled hard mask under etch process to generate free standing amorphous Si fins with widths as small as 20nm and heights of up to 100nm. Next a plasma-enhanced chemical-vapor deposition (PECVD) oxide is deposited over the trenches followed by a timed oxide CMP to open the tops of the Si fins. A highly selective dry etch then removes the Si fins leaving 20nm wide by 80nm deep trenches which can be used to evaluate advanced damascene processes. The application of these structures to the issues of advanced metallization is described further [see(Copper resistivity)].
Figure 4: Overview of a sacrificial fin flow, which is used to generate narrow trenches with a critical dimension down to 20nm.
Scaling of the dielectric constant: deposition and characterization
The scaling of the dielectric constant of organosilicate glasses is commonly achieved by adding carbon to the silica backbone in the form of methyl groups and by increasing the porosity. The resulting mechanical properties of the low-k material are, however, inferior to oxide. Additionally, porosity gives rise to the diffusion of moisture, chemicals, plasma species into the low-k material and these may interact with the low-k matrix. Consequently, processes have to be characterized in terms of their interaction with low-k dielectrics and adapted to optimize the modification of the low-k dielectrics.
In previous years, ultra-violet (UV) curing was used to modify the silica matrix with the aim to increase the matrix connectivity and/or the number of more energetically stable silica bonds. UV curing, however, also offers the possibility to remove porogens - sacrifical organic molecules that determine the amount of porosity in the matrix - efficiently in organosilicate glasses. With this approach it is possible to increase porosity such that k values of about 2.24 to 2.55 could be achieved with corresponding Young's moduli between 4.2 and 10GPa P15109, C15636. This is an important enabler for the integration of ultra low-k dielectrics into damascene structures.
The UV radiation interacts with both organosilicate matrix and the sacrificial porogen material. In order to better understand the different modifications of the film during different durations of the UV cure, Fourier transform infrared (FTIR) spectra in the 2800cm−1-3050cm−1 and in the 960cm−1 to 1350cm−1 were carefully investigated. Figure 5 left shows the first region of this spectrum. It is mainly composed of four peaks: two peaks around 2980cm−1 and 2900cm−1, related to CH3 groups, which are mainly attached to the silica matrix. The CH3 group is very important in order to maintain the film hydrophobic and with a low dielectric constant. The other 2 peaks at around 2930cm−1 and 2880cm−1 are related to CH2 groups, which are included in the porogen material. A deconvolution of the spectra shows that the removal rate of the CH2 groups for short cure times is much higher than of the CH3 groups, while after some time, the removal rates of both groups become similar. Removal of CH2 groups increases the porosity and hence decreases the dielectric constant. Removal of the CH3 groups increases cross-linking and it increases the dielectric constant. Therefore, an optimization of the cure time is necessary. Figure 5 right shows the FTIR spectra in the region where the Si-O bonds yield the signal. After deconvolution it becomes apparent that the Si-O cage peak (around 1140cm-1) decreases monotonically and very pronounced for the longer cure times. The Si-O network peak around 1065cm-1 increases monotonically, also more pronounced for the longer cure time. As a consequence, the mechanical properties will improve with cure time, as expected, and more pronounced for the longest cure time. However, this also indicates that the final structure will be more dense and hence the dielectric constant increases for this long cure time.
Figure 5: FTIR spectra related to the C-H bonds (left) and to the Si-O bonds (right) for an organosilicate film as a function of UV-curing time.
When combining the FTIR spectra for both regions, the 6 T cure would be the optimal compromise point as it still has a relatively high CH3 content, while most of the CH2 porogen groups have been removed and the network Si-O to cage Si-O ratio is relatively high.
Knowledge about which ultraviolet energies are most effective is still limited and the consequences of applying the UV cure process to integrated stacks in on-chip interconnects unknown. To clarify these open questions, the optical properties of a SiCOH low-k and a SiCHN barrier layer by purged UV spectroscopic ellipsometry in the energy region 2-9eV was investigated. The complex refractive index of the low-k film shows an absorption edge with a superimposed absorption band at 6.4eV that vanishes upon UV assisted curing. Comparison with FTIR demonstrates that the absorption at 6.4eV (~194nm) must be attributed to the organic porogens, which also influences the absorption edge. Further analysis reveals the red-shift of the absorption edge with increasing C atomic concentration C14834. The measured optical properties permit to simulate the standing-wave pattern of light within the films in differently configured stacks. The optical properties of the SiCOH low-k and the SiCHN barrier layers can be used as a reference and for the design of on-chip interconnects. Initial results from experiments with narrowband UV radiation on organosilicate materials indicate an efficient interaction of the radiation (wavelengths of 185nm and below) with the matrix resulting in enhanced cross-linking. Due to the fast conversion, it is, however, challenging to limit the loss of CH3 groups and, therefore, the increase in dielectric constant.
Zeolites are classically described as crystalline aluminosilicates containing pores and cavities of molecular dimensions. Aluminum-free versions of zeolites designated as silicalites are hydrophobic. These materials can reach a low dielectric constant due to the relatively low polarizability of the SiO2 matrix and their porosity. Moreover, as a consequence of their crystallinity they maintain good mechanical properties and good heat conductivity even at high porosity. Silicalite-1 with MFI framework topology is the most widely studied pure-silica zeolite being the Al-free analogue of ZSM-5 zeolite. All the intrinsic properties of pure-silica zeolites make them very attractive for future insulator materials (low-k materials) in on-chip interconnects: high porosity, small pore size, hydrophobicity, good mechanical properties, good heat conductivity and low dielectric constant. Yan et al. investigated the application of pure-silica zeolite films as low-k materials. They reported two kinds of approaches for pure-silica zeolite films deposition, i.e.. in-situ crystallization and spin-on. Because of the compatibility with the microelectronics industry, spin-on films appear to be more appropriate for the low-k application. Spin-on silicalite-1 films are deposited by spinning on a silicalite-1 nanoparticle suspension onto a Si wafer. The suspension is prepared by a hydrothermal treatment of a so-called `clear' solution, which contains primary silica nanoparticles of 3-5nm. Upon heating this evolves to a nanoparticle suspension which includes silicalite-1 nanocrystals and remaining primary silica nanoparticles. Despite the intrinsic hydrophobicity of silicalite-1, these films are hydrophilic. The reason is the use of silicalite-1 nanocrystals with low crystallization time, smaller than 100nm, presenting an important external surface area with silanol groups and the presence of residual primary silica nanoparticles which have a high concentration of hydroxyls. The silicate framework terminating Si-OH groups work as active sites for water adsorption, which results in a drastic increase of the dielectric constant of the films as well as in electrical leakage. A vapor phase treatment such as silylation decreases the hydrophilicity but presents drawbacks especially in microporous films because of pore blocking. Furthermore, the porosity is drastically decreased due to the silane compounds incorporated. The technique is also less convenient for implementation in microelectronic industry due to its long duration. Therefore, alternative hydrophobization treatments are necessary to develop spin-on silicalite-1 films for the low-k application. Recent research in the area of porous organo-silica glasses revealed that the combination of UV irradiation and thermal activation (so called UV-assisted cure) effectively generates a rearrangement in the bond structure. A new post-treatment method was developed to induce hydrophobization of spin-on silicalite-1 films during the removal of the organic template. It consists of a wide-band UV irradiation combined with thermal activation. Hydrophobization of the film is obtained because the UV treatment drastically decreases the quantity of silanols. Methylation of the silica surface is obtained by decomposition and reaction of the organic tetrapropylammonium template of the zeolite. The formation of cracks during the removal of the organic template is minimized P14832, P14833, C14853.
Scaling of the dielectric constant: integration
As pointed out in the previous section [see(Scaling of the dielectric constant: deposition and characterization)], methyl groups bonded to the silica network provide low-k and hydrophobic properties. As the methyl-silicon bond is the weakest bond in the organosilicate glasses matrix, it is prone to be severed during integration. Therefore, the biggest challenge in the integration of organoslicate glasses is to maintain the low-k and hydrophobic properties.
The most severe damage of low-k materials happens during their exposure to strip-cleaning plasmas containing oxygen and hydrogen radicals C15024, C15025, C15026, P15324, P15023, C15289, C15291, P15345. Recently, a diffusion-recombination model (Thiele analysis) was applied to predict and quantify the plasma damage of porous low-k materials. The penetration depth of radicals into porous low-k materials and the depth of plasma damage depend on the sum of reaction constants consuming active radicals on the pore wall, the diffusion coefficient and the pore diameter, respectively. The higher the Thiele modulus, the lower the depth of penetration of active radicals. Because the reaction constant is mainly defined by the recombination of active radicals, the depth of plasma damage can be significantly reduced by stimulating the surface recombination of active radicals. The creation of surface active centers initiates the recombination of oxygen and hydrogen radicals and reduces the plasma damage. As an example, treatment of low-k materials in He plasma was shown to significantly reduce plasma low-k damage during the subsequent exposure to strip and cleaning plasmas has been further characterized. The modification of the top part of low-k films with a dielectric constant of 2.5 that had been treated by He and NH3 plasmas. This plasma is normally used to clean the Cu surface and to reduce Cu oxides before dielectric barrier deposition. He plasma emits high-energy extreme UV photons, creating oxygen vacancies that localize chemical modifications in the top part of the film. The subsequent NH3 plasma treatment provides the complete sealing of the low-k surface. The thickness of the densified layer is close to 17nm. The depth of the modification is limited because of the high absorption coefficient of silica-based low-k materials in the range of EUV emission of the He plasma. The He plasma treatment also reduces plasma damage even when the low-k dielectric film is not sealed. If this is the case, the modified layer increases the recombination probability of active radicals and, therefore, decreases their concentration and depth of penetration into low-k materials. Properties of EUV emission from He and He/H2 plasmas can be very important in the development of technological processes with reduced damage during the plasma processing.
Another source of low-k modification is CMP. As the barrier is removed, the low-k is exposed to the mechanical action and the chemicals used. Surface hydrophilisation of pristine low k has been reported in previous annual reports as a CMP-induced damage mechanism. This phenomenon already enhanced by several factors (e.g. mechanical polishing action, solid content in the slurry, pH of the slurry solution, presence of organic residues, etc.) extends to bulk hydrophilisation when polishing metal/ultra-porous low-k (ULK) systems. The degree of bulk hydrophilisation depends on the nature of the selected metal/low-k combination, the metal being either a hard mask (for low damage patterning purposes) or a Cu diffusion barrier. The phenomenon is more or less pronounced depending on the nature of the overlaying metal film (Ta>TaN>Ti>TiN). It also correlates with the post CMP defects generation and more specifically with the presence of scratches with depths ranging from ~180nm down to ~6nm as measured with a 0.19μm tip depending on the metallic layer. These scratches can be reduced in number and depth by overpolishing leading thereby to reduced hydrophilicity. Besides selecting properly the overlaying metal film, UV curing the ULK for mechanical properties improvement and/or engineering the metal/ULK interface by inserting a thin dielectric layer with higher mechanical properties (termed dielectric protection layer - DPL) to prevent the metal from contacting the low-k surface, significantly limit the direct CMP-induced bulk hydrophylisation.
Figure 6: Number of defects and depth of defects on UV-cured porous dielectrics after removal of different metal layers by direct CMP.
The benefit of using a DPL in combination with a TaN metal hard mask (MHM) has been demonstrated for a medium porosity organosilicate glass dielectric. The DPL consisted of a dense organosilicate glass film with a k value of ~3.1-3.5 and a Young modulus of ~23GPa. The use of DPL gave rise to tighter resistance and capacitance distributions. This is due to a lower removal rate and Cu loss during CMP. It was also observed that the DPL layer impacts positively on the leakage and breakdown performances as evidenced by a reduction of 3 orders of magnitude in leakage current. Without DPL, significant changes in leakage current during thermal cycling are observed. This is attributed to moisture absorption and desorption in/from the ULK as a consequence of ULK scratching and hydrophilisation during direct CMP. This result suggests that the DPL protects the ULK film against this CMP-induced damage. Time-dependent dielectric breakdown (TDDB) measurements are subsequently carried out at 100°C. Without DPL a very short lifetime is obtained, while with DPL a lifetime over 10 years under user conditions, was achieved C15356.
Specific environmental conditions can accelerate the cohesive failure rate of organosilicate glass films. In particular, the acceleration in basic ambients has been highlighted, due to the weakening of the silica bonds through a stress corrosion mechanism governed by OH- species. In channel cracking, no external force is applied to the film, the driving force is given by the residual stress of the film. As a rule, the cracking rates in solutions are considerably higher than in room ambient. Further, the cracking rates are exponentially affected by the pH of the wet medium. It was further confirmed that the pH of the solution is the principal parameter governing the acceleration by comparing solutions with different composition and same pH. Therefore, the use of a corrective factor in the expression of the driving force for channel crack propagation was proposed to account for the environmental effect C14406. The corrective factor is a function of the pH of the solution. This phenomenon is of major relevance for interconnects manufacturing, where processing solutions are regularly used, i.e., for cleaning purposes. Process steps like CMP, where wet ambients are used in combination with the application of a mechanical force, are particularly critical. In this case, an appropriate choice of the pH of the process medium is essential.
Key technology features must be considered to enable direct CMP of high porosity low-k materials. These factors include (1) ULK surface engineering to enhance the mechanical properties and thereby the resistance against scratches caused by the `harder' metal particles/agglomerates, (2) UV-curing the low k to improve its mechanical properties, and (3) carefully selecting the metal layer. Following these recommendations, the MHM concept with TiN to minimize plasma-induced damage during patterning can be further extended to fabricate dual-damascene structures.
In order to provide a test vehicle for integration options, a dual-damascene flow has been created with a porous dielectric (k=2.5) with the design rules for the 65nm technology node. The process flow utilizes a TiN metal hard mask to reduce the plasma damage to the low k, which enables a partial trench first approach. Good parametric yield has been achieved with via structures with both high and low via density.
Figure 7: Distribution of the resistance of via structures with different numbers of vias and cross-sections of an electromigration structure with an isolated via (top photo) and a via chain with a high via density (bottom photo).
Air is regarded as the ultimate low-k material. Air gap formation on 300 mm-size wafers was demonstrated based on UV-assisted decomposition of a sacrificial film deposited by CVD. The scheme increases the damascene integration processing by one step: the decomposition of the CVD sacrificial material, which occurs after completion of the standard process by (CMP). First, the dielectric stack was deposited by CVD. The stack consisted of a sacrificial porogen material, followed by a hard mask, both deposited at the same temperature in a two-step process. The hard mask material was an organosilicate glass-type low-k dielectric that, if it is UV-treated, results in ~15% porosity and a dielectric constant of 2.8. The deposition was followed by lithography, dry etch, metallization and CMP. After CMP, the sacrificial material was decomposed at 420°C under UV-light in a He atmosphere. The UV illumination accelerates the decomposition process. After decomposition, the air gap occupied ~60% of the area between the Cu interconnects. Scanning electron microscopy (SEM) images from samples after air gap formation are shown in figure 8 . Simultaneous formation of air gaps in wide and narrow spacings was achieved across the wafer. The spacings are stable up to a width of 2μm.
Figure 8: Cross-section images of single-damascene airgap structures, which were created by UV-assisted removal of a thermally decomposable material. Width/spacings a) 100nm / 100nm and b) 500nm / 500nm with passivation on top.
Barrier and seed
The role of wetting and surface diffusion of Cu on barrier materials is of critical technological importance because it is closely linked to the reliability behavior of Cu interconnects, such as electromigration, stress-induced voiding and TDDB. Wetting experiments are widely used to investigate the interactions of Cu on refractory barrier materials, but no work reports on quantitative studies about surface diffusion along Cu/barrier material interfaces. Ta barrier material is selected because it presents a relevant scientific and technological interest as a Cu diffusion barrier in interconnect technology. Ta exists in two phases, a low-resistivity α-phase (α-Ta, body centred cubic, space group: Im3m) and a high resistivity β-phase (β-Ta, tetragonal, space group: P42/mnm). The surface diffusion coefficient of Cu (DS) was measured on alpha and beta Ta substrates. Thin Cu films deposited on Ta substrates were annealed at various temperatures for various times leading to the formation of clusters. The kinetics of cluster growth was followed experimentally and the theory developed by Geguzin and al. was used to calculate the surface diffusion coefficients. The surface diffusion coefficients of Cu on α-Ta and β-Ta were measured for the first time. It was observed that Cu surface diffusion is slower on α-Ta than on β-Ta. The quantitative understanding of the surface diffusion mechanism emerging from these studies is one important step towards the understanding of the reliability behavior of Cu interconnect lines P15328.
Figure 9: Surface diffusion mechanisms: (a) the diffusion occurs as Cu adatom surface diffusion on the Cu mono-layer; (b) the diffusion occurs as Cu surface diffusion on the Ta surface via vacancy in the Cu monolayer. SEM images of a Cu film on β-Ta substrates after annealing at 550°C for 1029 seconds in vacuum and without air-break (in-situ). Arrhenius plot of the surface diffusion coefficient vs. the inverse temperature for Cu on two types of Ta substrate surfaces (α and β Ta).
It is difficult to obtain conformal barriers of nm dimensions foreseen in future device architectures without resorting to novel materials and unconventional methods. To this end, the self-assembly of molecular layers composed of organic chains terminated with desired functional groups is attractive for modifying surface and interfacial properties for a variety of micro- and nano-electronic applications. The atomically controlled surface chemistry and structure of self-assembled monolayers (SAMs) provide a means of creating model organic and inorganic thin films in the nm regime. A range of SAMs has been explored for inhibition of interfacial Cu diffusion and promotion of Cu-SiO2 adhesion. A selective process for Cu dual-damascene integration is presented using SAMs as a sacrificial passivation layer and as a diffusion barrier as illustrated in figure 10. The choice of the barrier layer is investigated in detail using a multitechnique characterization approach. The influence of alkyl chain length (n = 7 to 22), head group (Y = Cl3 or (OCH3)3) bonding to the substrate and variation of the terminal functionality (X = CH3, CN, Br, SH, NH2, C5H4N) on Cu adhesion and diffusion is evaluated by systematic variation of the molecular structure of SAMs derived from X(CH2)nSiY. In general, it was found that even with terminal groups that are relatively reactive towards bonding Cu, e.g., thiol groups (SHs), SAMs with methoxy head group bonding to the substrate show poor inhibition of silicide formation, attributed to their relatively low thermal stability and less dense packing compared with trichloro-derived SAMs. For example, x-ray diffraction (XRD) data confirms Cu silicide formation at 200ºC upon annealing a Cu film deposited on a 3-mercaptopropyltrimethoxysilane derived SAM compared with inhibition to above 400ºC with a SAM formed from 11-cyanoundecyltrichlorosilane. Cu adhesion shows the opposite trend. In selecting a barrier, trichlorosilanes are promising due to their high thermal stability (above 550°C) and dense molecular packing. Overall, this study demonstrates that the tuneable structure and chemistry of SAMs provides a molecular level engineering approach for future device structures.
Figure 10: A selective self-assembly process for formation of a SAM barrier to Cu diffusion in dual-damascene integration: (a) non-selective barrier SAM-B formation on SiO2 and Cu surfaces, (b)sequential immersions resulting in selective sacrificial SAM-S passivation of Cu surfaces followed by barrier SAM-B formation on SiO2 surfaces, and (c) thermal release of SAM-S.
The incorporation of Al into the Cu seed layer is known to improve the quality of the ALD TaN/Cu interface and improve the reliability performance of the interconnect. The drawback of alloying the Cu is a possible increase in Cu resistivity. It was therefore investigated whether amounts of Al smaller then the usually reported 1-2% would limit the resistivity increase C15351. In the case of seed layers as thick as 60nm (baseline thickness for IMEC's 65nm technology node), an increase in resistivity proportional to the amount of Al incorporated is noticed. The incorporation of 0.2 at. % of Al into the seed layer leads to a minor increase in resistivity which is still acceptable from technology point of view (~1-2%), whereas the use of 1 at. % of Al impacts the resistivity negatively with an unacceptable increase of ~ 5% compared to the reference. This uniform increase in resistivity over different line widths could relate to smaller grains. The incorporation of 0.2 at. % aluminum into the seed layer does not seem to affect too much the grain growth of the Cu in the lines as the measured Cu resistance is quite comparable to those measured for lines using pure Cu seed layers.
The thinning of the Cu seed layer in narrow trenches raises questions about the scalability of this approach. Ruthenium (Ru) is a candidate to replace Cu as a substrate for plating as its oxide is conductive. Because the sheet resistance of ruthenium is higher than of Cu, the terminal effect plays an important role for the direct Cu plating process on Ru. The right choice of the suppressor is crucial in enabling full coverage of Cu on Ru. SEM images in figure 11 show that Cu islands density is higher when the suppressor is present in the bath, and that islands start coalescing after 45 seconds. These observations suggest that the suppressor adsorbs onto nucleated Cu islands, inhibits their growth, and thus promotes nucleation of new Cu islands in their vicinity. Once the islands coalesce, nucleation is arrested and larger overpotential is needed to keep the current constant. Potential transients together with ex situ SEM could prove to be a powerful tool for studies on nucleation and growth phenomena on resistive substrates C14842.
Figure 11: (a) Potential transients after 5, 15 and 45 seconds of Cu deposition on Ru (8nm thick) at -5mA cm-2 from 0.24 M CuSO4, 5H2O, 1.8M H2SO4, and 1.4mM HCl, without and with a suppressor additive. Also shown are corresponding SEM images of Cu islands deposited on Ru from the sulfate bath with no additives (b) and with the suppressor (c).
Copper resistivity
It is well established that the down scaling of Cu interconnects results in a dramatic increase in Cu line resistance. As Cu resistance rises non-linearly with Cu line width, shrinking below 100nm becomes very challenging due to an increasing contribution of electrons scattering from mainly the sidewalls but also from grain boundaries of the wires, as the Cu line dimensions become comparable to the electron mean free path (~ 40nm at 300K). The resistance of Cu interconnects represents a significant contribution to the signal delay. Therefore, the resistivity increase of narrow Cu lines will seriously impact the RC delay and will limit signal propagation in integrated circuits.
The fabrication of narrow Cu trenches using a conformal tetraethyl orthosilicate (TEOS) backfill resulted in Cu trenches with widths down to 30-40nm. With an adequate Ta-based PVD barrier & Cu seed layer scheme, narrow Cu lines with high yield were obtained. An increase of the electrical resistivity in the narrowest dimensions was observed as a result of the size effect for both barriers (bilayer TaN/Ta versus Ta) investigated. Electron backscattering diffraction (EBSD) analysis was carried out to determine grain orientation and texture in narrow Cu trenches. For the first time, EBSD data reveal that Cu trenches down to 30-40nm wide have mostly a random texture. The narrower the Cu lines, the weaker the (111) texture with both monolayer and bilayer Ta-based barriers. This can be attributed to the increased influence of the sidewalls in narrower trenches P15358.
In order to investigate trenches with dimensions smaller than 40nm, a sacrificial Si fin flow had been devised, which has been described elsewhere [see(Pitch and CD scaling of damascene structures for the 22 and 32nm technology nodes)] (see figure 4). Barrier/seed/electroplating processes had to be developed to generate void free trenches. In this study both atomic layer deposition (ALD) TaN and thin resputtered physical-vapor deposition (PVD) TaN/Ta barriers were investigated in addition to variations in seed sputter bias and electroplating accelerator levels. To improve the adhesion of the ALD barriers, a 1 nm in-situ PVD Ta Flash layer was deposited immediately after the ALD TaN layer deposition. The parametric yield of structures from 25 to 925nm widths are presented in figure 12. There is clearly both a strong width dependence on the yield and a high variability in the resistance, particularly for the narrowest structures. It is encouraging though that the yields for even 35 and 25nm test structures are 45% and 15%, respectively, enabling meaningful extractions of resistivities for such narrow and short lines. As mentioned earlier, these wafers have a large trench height variation which is largely responsible for the wide spread in resistance for structures of all widths. Figure 12 presents the extracted Cu resistivity versus trench width using the corrected Matthiessen's rule for both the PVD and ALD samples. A constant trench height of 69nm was assumed for all trenches, extracted from the surface area of the largest trenches divided by their nominal width from top-down SEM measurements. Clearly there is an increase of resistivity from 2.9 to 3.5 with decreasing width. The resistivities of the lines with PVD and ALD barriers appear to be comparable, with the PVD showing more scatter perhaps due to internal voiding. For comparison, a similar theoretical curve assuming p=0 and no grain boundary scattering is also presented. The similarity between the experiment and theory is important to note the expected large variation in grain structure and apparent lack of grain boundary scattering in the data. More statistically significant measurements and TEM cross sections of these structures are required before more quantitative assessments of resistivity scaling can be made.
Figure 12: Resistance distribution as function of nominal line width for a wafer processed with ALD and PVD barriers. Cu resistivity as a function of trench width (left). The resistivity and cross sectional area are extracted electrically from applying Matthiessen's rule and a height of 69nm is assumed for all lines (right).
Integration of copper in contacts
With the down-scaling of contact sizes, contact resistance, which is inversely proportional to contact area, will increase to a level comparable to transistor resistance, traditionally dominated by channel components, junctions and silicide/junction contact resistance, and result in higher switching delay. Especially on circuits where the possibility for redundant contact placement is limited, this can lead to a non-negligible contribution to the parastics, approaching the junction resistance and thereby affecting the device performance. In Scientific Report 2006, it was reported that the resistance increase can be delayed by at least one technology node by replacing the incumbent tungsten contacts with Cu ones. IMEC's 130 nm CMOS technology platform was used for this demonstration. Recently Cu contacts have been scaled in critical dimension and pitch and have been implemented in IMEC's 65nm CMOS technology platform.
Obviously the main concern linked to Cu contacts is the impact on the reliability of underlying devices due to the high diffusive nature of Cu in Si and its tendency to form harmful Cu-silicates. Since a thick enough barrier at the bottom is required for reliability, while barrier thinning is needed for lower contact resistance and scalability, the minimum required barrier thickness to prevent Cu diffusion was evaluated by the formation of a Cu silicide P15357, C15361. For this purpose the formation of Cu-silicide related XRD peaks upon an in-situ variation of the sample temperature was monitored for blanket wafers with various Cu/barrier metal stacks on NiSi. It was found that silicidation was initiated only on wafers heated to temperatures above 500°C for Ta barriers as thin as 2.5nm. In the absence of a barrier the failure temperature dropped below 200°C. The same study was made for an ALD TaN barrier layer where it was shown that a 4nm layer was sufficient to prevent Cu diffusion, while for 2 and 3nm the failure temperature was moving closer to the thermal budget used in the integration process. Below 2nm the effectiveness of this barrier was found to be poor. On a next level of evaluation, the integrity of the barriers in contact patterns was investigated. A minimum thickness of about 5nm for both ALD or PVD barriers was required at the bottom of the contact holes in order to prevent silicide formation.
On one hand, the contact resistance using pure ALD TaN is prohibitively high for this critical thickness. On the other hand, it is challenging to obtain yield with PVD barriers particularly in deep contacts due to the limitations of the PVD barrier with regard to bottom and sidewall coverage. As reliable Cu contacts require good bottom coverage, whilst maintaining sufficient sidewall coverage, a combination of both PVD barrier (good bottom coverage) and thin ALD barrier (good sidewall coverage and limited impact on contact resistance) has been explored. In figure 13 the contact resistance obtained on gate contacts for a stand alone 6nm ALD TaN barrier, the 28nm process of record (POR) PVD TaN/Ta barrier and two hybrid schemes are shown. On top of the ALD TaN film each time a PVD-Ta Flash layer was deposited for improved adhesion to the Cu. While for barrier layers up to 4nm, no yielding structures could be fabricated (results not shown here), the result on the 6nm film confirms that this thick ALD deposit is finally capable of acting as a Cu barrier during integration. However, as expected, the penalty in terms of contact resistance is severe. The insertion of a PVD underlayer results in a drastic decrease of the contact resistance value and uniformity, up to a factor of 10, without yield loss. Assuming the silicide/barrier interface resistance is similar for splits where a PVD Ta layer is in contact with the silicide allows for a rough estimation of the resistivity of the integrated ALD TaN film on PVD Ta. At variance with what is reported for ALD TaN on oxide, the resistivity of the film as grown on PVD Ta is orders of magnitude lower: 1.5mΩcm versus 100mΩcm. On TEM images the three constituent layers can be clearly identified. Notice as well the contrast difference for the ALD TaN layer on the contact bottom when grown on Ta versus directly on NiSi. Taking into account the PVD Ta Flash layer on top, the ALD thickness on bottom and sidewall as derived from TEM is significantly lower than the expected value of 6nm. Although the final contact resistance value for this approach is still somewhat higher than what is obtained on the thick PVD Ta(N) counterpart, and the performance on S/D contacts remains to be checked, further optimizing the individual layer thickness of PVD and ALD layers opens perspectives for a more scalable route to successfully integrate sub-90nm Cu contacts C15028.
Figure 13: Resistance per 90nm contact on a chain of 100 contacts for PVD and ALD stand alone barriers + hybrid barrier schemes. TEM on the integrated 90nm contacts for the ALD TaN stand-alone and PVD/ALD hybrid barrier.
Low-k dielectric reliability
(see section Low-k dielectric reliability)
Electromigration and stress-induced voiding
(see section Electromigration and stress-induced voiding)