CMOS scaling
Strategy
Lithography IIAP
Advanced lithography
Immersion lithography extendibility
Double patterning lithography
EUV lithography
Resist fundamentals
Planar IIAP
Strategy
Ultra-shallow junctions
Silicides
Channel engineering
Gate dielectric
Poly electrode
Baseline process
Emerging alternative devices (EMERALD) IIAP
Strategy
Unit process step development for MuGFETs
Multi-gate devices (MuGFET)
Small circuit demonstrators using multi-gate devices
Interconnects IIAP
Strategy
Cu/low-k interconnects
3D IIAP
3D Design
3D-SIC: stacked ICs
3D WLP (through-silicon via technology)
Flash memory IIAP
Strategy
Floating-gate devices
Nitride-based technology
Ultra-clean processing IIAP
Strategy
Ultra-clean processing program: cleaning for FEOL applications
Ultra-clean processing program: cleaning for BEOL applications
Ultra-clean processing program: generic aspects
Germanium/III-V IIAP
Strategy
Ge MOS devices
III-V MOS devices
Post-CMOS nanotechnology IIAP
Strategy
Semiconducting wires
Tunnel FETs
Carbon nanotubes
Graphene
CMOS-based heterogeneous integration (CMORE)
Strategy
BiCMOS technology
SiGe MEMS
MEMS reliability
RF-CMOS front-ends
Silicon photonics
Advanced Packaging and Interconnect Center (APIC)
Strategy
RF-integrated passives system-in-a-package technology
Above-IC RF technology
Multilayer-thin-film
RF-MEMS and RF-MEMS packaging
3D-wireless system integration
3D interconnect and packaging
3D systems in-a-package (SiP)
3D-SIC: stacked ICs
3D-WLP: micro-bumping
3D-WLP: ultra-thin-chip stacking (UTCS)
Advanced chip package solutions
Next-generation flip-chip and substrate technology
Ultra-thin-chip stack (UTCS) and ultra-thin-chip flex (UTCF)
Optical interconnects and sensors
Large-area electronics
Nomadic Embedded Systems (Apollo)
Strategy
Software-defined radio front-end
Software-defined radio baseband
ADC solutions
Cognitive radio solutions
60GHz communications
Cross-layer (Quality of Experience)
Multimedia
Multi-processor system-on-chip (MPSoC)
Power-efficient compiler technology and processor architectures
Technology-aware design (TAD)
Photovoltaics (Solar+)
Strategy
Si-based photovoltaics
Photovoltaic stacks
Organic photovoltaics
GaN and III-V technologies (Power electronics)
Strategy
GaN epitaxial layer growth
GaN device processing
GaN system integration
Biomedical electronics
Strategy
Smart implants technology
Body area networks
Brain-computer interface
Molecular imaging, diagnostics and therapy
Organic electronics
Strategy
Organic devices
Organic photovoltaics
Organic electronics
Wireless autonomous transducer solutions (WATS)
Strategy
Ultra-low-power radio
Ultra-low-power DSP
Sensors and actuators
Micropower generation and storage
Human++: body area networks
Scientific report 2007
Program strategies and related results
CMOS scaling
Interconnects IIAP
Contact:
sreport@imec.be
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