Unit process step development for MuGFETs
Gate stack
The metal gate of choice for the multi-gate field-effect transistor MuGFET devices is still TiN. The impact of different deposition techniques for the TiN film on MuGFET devices has been evaluated. In parallel, HfSiO-based high-k gate dielectrics deposited by metal-organic chemical-vapor deposition (MOCVD) and atomic-layer deposition (ALD) deposition techniques were compared. Because of the lower conformality of the MOCVD HfSiO deposition process, the dielectric thickness on FIN sidewalls is significantly thinner as compared to planar devices.
The gate profile on the FiN sidewall was significantly improved by optimization of the gate-etch chemistry.
In ultra-thin FiN MuGFETs, the threshold voltage is determined mainly by the work function of the gate electrode. A mid-gap TiN gate sets up a MuGFET threshold voltage around +/-0.5V. Low threshold voltage required in high-performance applications can be obtained with the work function (WF) engineering. The gate patterning and high-k removal processes were optimized to evaluate the different WF modulation techniques: As and Al implantation into TiN, dielectric capping and TiN thickness modulation.
Junction formation
Reduction of the access resistance in MuGFETs is another major concern. For better measurements and analysis of SD resistance in narrow fins a new secundatry ion mass spectrometry (SIMS)-based technique was developed to characterize the dose implanted on the top and at the sidewalls of the fin in an efficient way. Next to that, amorphization and problematic recrystallization of the junctions have been identified as the most critical issues in MuGFET junction formation. Transmission electron microscopy (TEM) analysis revealed the existence of defects after anneal in the junction regions and the formation of poly grains .
Figure 1: Cross-sectional transmission microscopy (XTEM) of a narrow fin after HDD implantation and anneal.
The use of P3I (plasma doping) was investigated further through short-loop experiments (resistors) and integration at device level. First pMOS devices with conformal junctions formed by BF3 plasma doping were demonstrated. The performance of the P3I devices matches with conventional junctions implanted with the 45° tilt, indicating that the P3I junctions are very promising for dense structures where the implantation tilt is limited.
For the S/D Si selective epitaxial growth (SEG) process, the impact of the extension amorphization and thus implant conditions on the SEG growth rate has been studied extensively.
Strain engineering
The use of mobility engineering techniques like strained silicon on insulator (SSOI), stress memorization technique (SMT) and strained contact etch stop layer (CESL) on MuGFET were further investigated. One of the most efficient ways of introducing strain into both planar and multi-gate devices is the use of intrinsically strained nitride layers. The boost in performance for the nMOS is significant when using tensile CESL. It has also been demonstrated that tensile CESL can be used on pMOS as well without degradation of the current.