Gate dielectric
As mentioned in (see section Gate stack), an enabling process for achieving low VT high-k/metal-gate (HK/MG) transistors is the use of dielectric capping layers. It has been demonstrated by several groups that a large WF shift can be obtained by modifying the metal/dielectric or dielectric/interfacial oxide interfaces. When using Hf-based bulk dielectrics, this can be done quite effectively using a thin (typically 0.5nm to 1.0nm) La2O3 layer towards the conduction band and Al2O3 towards the valence band. This is illustrated in figure 1 that shows the flatband voltage (VFB) shift obtained when inserting such capping dielectric P14227, P14321. Atomic layer deposition (ALD) processes have been developed for both capping materials. These are well-behaved as illustrated by the growth curves in figure 2 C15422, C15428, C15697, C15698. While ALD cap processes was the main dielectric development focus in 2007, the bulk dielectric process was continued C15698, C15699, P14509, P15706, P15707, P15708.
Figure 1: Impact of LaO capping on nMOS metal WF (left) and of AlO capping on pMOS metal WF (right).
Figure 2: Growth curves of both LaO and AlO ALD deposition processes.
This dielectric modification raises a legitimate concern with respect to the mobility and reliability of such devices. However, it was found that the stacks can be optimized to maximize the VFB shift while minimizing detrimental mobility and reliability effects. In figure 3 , the VT shift, peak mobility and positive bias temperature instability (PBTI) are plotted as function of capping layer thickness. An optimum is found around 0.5nm where PBTI and mobility are acceptable and a ~400mV VT shift can still be obtained C14601. It was also have found that Al2O3 capping has a small impact on mobility when used on non-nitrided HfSiO bulk dielectric and has acceptable time-dependent dielectric-breakdown (TDDB) characteristics .
Figure 3: LaO thickness impact on VT shift, PBTI and mobility.
Figure 4: AlO capping impact on mobility and TDDB.
The impact of the thermal budget on the electrical properties of the metal/capping/bulk dielectric stacks has also been studied by applying milli-second anneal with various power. It was found that there is a VT, EOT and JG benefit in applying the highest power, as shown in figure 5 C14597.
Figure 5: Impact of milli-second anneal thermal budget on EOT, VT and gate leakage (JG).
Besides La2O3 and Al2O3, an atomic vapor deposition (AVD) process for depositing Dy2O3 films has been developed, which is also suitable as a dielectric capping layer C14587, P15014.
The use of capping layers enables to simplify further the HK/MG CMOS integration scheme from the dual metal, dual dielectric (DMDD) flow to the single metal, dual dielectric (SMDD) flow introduced elsewhere in (see section Gate stack). If one can selectively remove capping materials from the bulk dielectric and from each other, it is possible to define more simple integration flows that necessitate only 1 metal deposition and 1 bulk dielectric deposition. Future work will focus on this approach to quantify the impact of each process step on the electrical properties of the fabricated devices.
Figure 6: Proposed integration flow for simplified SMDD HK/MG CMOS.
closeC14587Chang, V.; Ragnarsson, L.; Pourtois, G.; O'Connor, R.; Adelmann, C.; Van Elshocht, S.; Delabie, A.; Swerts, J.; Van der Heyden, N.; Conard, T.; Cho, H.; Akheyar, A.; Mitsuhashi, R.; Witters, T.; O'Sullivan, B.; Pantisano, L.; Rohr, E.; Lehnen, P.; Kubicek, S.; Schram, T.; De Gendt, S.; Absil, P. and Biesemans, S. A Dy2O3-capped HfO2 dielectric and TaCx-based metals enabling low-Vt single-metal-single-dielectric gate stack. In: Technical Digest International Electron Devices Meeting - IEDM. 2007. pp.535-538; (10-12 December 2007; Washington, DC, USA.)
closeP15014Adelmann, C.; Lehnen, P.; Van Elshocht, S.; Zhao, C.; Brijs, B.; Franquet, A.; Conard, T.; Roeckerath, M.; Schubert, J.; Boissiere, O.; Lohe, C. and De Gendt, S. Growth of dysprosium-, scandium-, and hafnium-based third generation high-k dielectrics by atomic-vapor deposition. Chemical Vapor Deposition. Vol. 13: 567-573; 2007.
closeC14597Kubicek, S.; Schram, T.; Paraschiv, V.; Vos, R.; Demand, M.; Adelmann, C.; Witters, T.; Nyns, L.; Ragnarsson, L.; Yu, H.; Veloso, A.; Singanamalla, R.; Kauerauf, T.; Rohr, E.; Brus, S.; Vrancken, C.; Chang, V.; Mitsuhashi, R.; Akheyar, A.; Cho, H.; Hooker, J.; O'Sullivan, B.; Chiarella, T.; Kerner, C.; Delabie, A.; Van Elshocht, S.; De Meyer, K.; De Gendt, S.; Absil, P.; Hoffmann, T. and Biesemans, S. Low VT CMOS using doped Hf-based oxides, TaC-based metals and laser-only anneal. In: Technical Digest International Electron Devices Meeting - IEDM. 2007. pp.49-52; (10-12 December 2007; Washington, DC, USA.)
closeC14601O'Sullivan, B.; Mitsuhashi, R.; Pourtois, G.; Chang, V.; Adelmann, C.; Schram, T.; Ragnarsson, L.; Van der Heyden, N.; Cho, H.; Harada, Y.; Veloso, A.; O'Connor, R.; Pantisano, L.; Yu, H.; Groeseneken, G.; Absil, P.; Biesemans, S.; Ikeda, A. and Niwa, M. Oxygen-vacancy-induced Vt shift in La-containing devices. In: Solid State Devices and Materials. 2007. pp.372-373; (19-21 September 2007; Tsukuba, Japan.)
closeC15698Delabie, A.; Nyns, L.; Bellenger, F.; Caymax, M.; Conard, T.; Franquet, A.; Houssa, M.; Lin, D.; Meuris, M.; Ragnarsson, L.; Sioncke, S.; Swerts, J.; Fedorenko, Y.; Maes, J.; Van Elshocht, S. and De Gendt, S. Atomic layer deposition of hafnium based gate dielectric layers for CMOS applications. In: Atomic Layer Deposition Applications 3. 2007. pp.227-241; (7-12 October 2007; Washington, DC, USA.) (ECS Transactions; Vol. 11, issue 7)
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closeP14509Cho, M.; Degraeve, R.; Pourtois, G.; Delabie, A.; Ragnarsson, L.; Kauerauf, T.; Groeseneken, G.; De Gendt, S.; Heyns, M. and Hwang, c. Study of the reliability impact of chlorine precursor residues in the Atomic Layer Deposited HfO2 layers. IEEE Trans. Electron Devices. Vol. 54: (4) 752-758; 2007.
closeP15706Vellianitis, G.; Petry, J.; Hooker, J.; Delabie, A. and De Gendt, S. Reliability degradation of HfSiO gate dielectric layers: influence of nitridation . Microelectronic Engineering. Vol. 84: (9-10) 1972-1975; 2007. (INFOS)
closeP15707Fedorenko, Y.; Swerts, J.; Maes, J.; Tois, E.; Haukka, S.; Wang, C.; Wilk, G.; Delabie, A.; Deweerd, W. and De Gendt, S. Atomic layer deposition of hafnium silicate from HfCl4, SiCl4, and H2O . Electrochemical and Solid-State Letters. Vol. 10: (5) H149-H152; 2007.
closeP15708Delabie, A.; Pourtois, G.; Caymax, M.; De Gendt, S.; Ragnarsson, L.; Heyns, M.; Fedorenko, Y.; Swerts, J. and Maes, J. Atomic layer deposition of hafnium silicate gate dielectric layers . Journal of Vacuum Science and Technology A. Vol. 25: (4) 1302-1308; 2007.
closeC15422Swerts, J.; Fedorenko, Y.; Maes, J.; Tois, E.; Delabie, A.; Ragnarsson, L.; Yu, H.; Nyns, L.; Adelmann, C. and Van Elshocht, S. ALD La-based oxides for Vt-tuning in high-k/metal gate stacks. In: Atomic Layer Deposition Applications 3 Atomic Layer Deposition Applications 3. 2007. pp.201-211; (7-12 October 2007; Washington, DC, USA.) (ECS Trans.; Vol. 11, iss.e 7)
closeC15428Van Elshocht, S.; Adelmann, C.; Conard, T.; Delabie, A.; Franquet, A.; Lehnen, P.; Nyns, L.; Richard, O.; Swerts, J. and De Gendt, S. Thermal stability of rare earth oxides as high-k gate dielectrics. In: 54th AVS International Symposium and Exhibition. 2007. (14-19 October 2007; Seattle, WA, USA.)
closeC15697Maes, J.; Swerts, J.; Tois, E.; Delabie, A.; Adelmann, C.; Ragnarsson, L. and Yu, H. ALD La2O3 cap layers on high-k gates to modify the metal gate work function. In: AVS Topical Conference on Atomic Layer Deposition - ALD. 2007. (24-27 July 2007; San Diego, CA, USA.)
closeP14227Ragnarsson, L.; Chang, V.; Yu, H.; Cho, H.; Conard, T.; Yin, K.; Delabie, A.; Swerts, J.; Schram, T.; De Gendt, S. and Biesemans, S. Achieving conduction band-edge effective work functions by La2O3 capping of hafnium silicates. IEEE Electron Device Letters. Vol. 28: (6) 486-488; 2007.
closeP14321Chang, S.; Yu, H.; Veloso, A.; Lauwers, A.; Delabie, A.; Everaert, J.; Kerner, C.; Absil, P.; Hoffmann, T. and Biesemans, S. The application of an ultra-thin ALD HfSiON cap layer on SiON dielectrics for Ni-FUSI CMOS technology targeting at low power applications. IEEE Electron Device Letters. Vol. 28: (7) 634-636; 2007.
