Double patterning lithography
The extension of 193nm water immersion lithography towards the 32nm half-pitch (hp) node and below requires patterning features at an effective k1 below 0.25, even when approaching the practical limit of 1.35 numerical aperture (NA). Crossing this physical limit is only possible when splitting the design on two masks to relax the minimum pitch, together with implementing a double patterning (DP) integration flow. This approach raises new challenges for mask design, imaging and integration flows. It will also lead to tighter specifications for scanner error budgets, e.g. for overlay.
Integration flows
A baseline double line process based on a single hard mask process has been established. This process has been used to measure and optimize the critical dimension uniformity (CDU) and overlay for the 32nm node on NA=1.2 and 1.35 scanners. It is also used developing DP-specific optical proximity correction (OPC) and to find process-induced design split limitations C12961, C15247.
For interconnect layers, a baseline double trench process has been developed for 50nm half pitch layouts using NA=0.85, and for 30nm half pitch layouts using NA=1.2 . Shrink techniques are necessary to pattern these small trenches. Both chemical and plasma-based shrink techniques have been developed for this purpose C12958, C12977.
Figure 1: 30nm hp single damascene patterning into a metal hard mask (MHM) using NA=1.2, quasar illumination. The left picture shows Litho2 on top of Etch1 topography (planarized using bottom anti-reflective coating (BARC)). The right picture shows the 30nm 1:1 pattern afterEetch2 and resist strip. This pattern can then be transferred into the underlying low-k material.
In order to make DP more cost effective than the current existing litho-etch-litho-etch scheme, new resist and integration schemes need to be developed, avoiding the intermediate etch C15373. Resist freezing techniques have become available which allow to coat and pattern a 2nd resist layer on top of already defined resist features. Several resist suppliers are following different approaches to explore these techniques. The combination of resists with different solvent systems allows the coating of the 2nd resist right on top of the 1st patterns. This was achieved by combining positive tone and negative tone resists. Freezing can also be obtained by coating a hardening layer on top of the 1st pattern, which makes it insoluble in the 2nd resist coat . Using a resist that can be cross-linked by flood exposure/bake before coating the 2nd layer is a third approach under investigation. Double development using a combination of positive tone and negative tone developer is an alternative for spacer defined double patterning approaches, which are commonly used in NAND Flash designs.
Figure 2: 36nm hp lines patterned using NA=1.2, annular illumination. 193nm resist is used and a freezing material was coated over Litho1 (36nm lines at 144nm pitch) before applying Litho2 (again 36nm lines at 144nm pitch).
Design split and OPC
The design split of 2-dimensional patterns into two separate layers is an important key for the success of DP. Full chip designs need to be split in an automated way when this technique is to be used in production. Therefore IMEC has been working with electronic design automation (EDA) vendors that develop this software C15836, C15840.
Automated polygon colouring - or distributing polygons on two separate masks - is used to define the split of the design. Split and OPC of a logic cell has to eliminate sub-resolution pitches and small spaces. Critical points for this split are stitching at the polygon cuts and possible process asymmetry. Some colouring conflict loops result from over-constrained polygon topologies, only resolvable through accounting for Double Patterning during the design stage C15841. A test mask has been designed for the study of split and design guidelines of 32nm node random logic applications.
DP printability through process variations (including mask error and overlay) is used to establish guidelines for design split and stitching robustness; it can also be used to guide the designer towards split-compliance. Sufficient overlap is required at stitching points, while that overlap can be constrained by pattern density and mask restrictions.
Process control and manufacturability
It has been demonstrated that on NA=1.2 scanners, CD uniformity values of 4.5nm across a full wafer can be obtained for 32nm dense (horizontal and vertical) lines without special corrections. Using local dose corrections for the systematic errors, CDU below 3nm can be achieved. Using the baseline process, overlay mean + 3σ as low as 4.5nm (combined X and Y) has been obtained without special corrections for a single wafer .
Figure 3: DP overlay for 32nm half pitch lines, exposed on a 1.2NA scanner. Mean + 3σ = 4.5nm, for combined X and Y data.
Because the overlay requirements for the 32nm are very stringent, it is important to identify any process steps, which could potentially introduce wafer deformation or influence the alignment mark stack transparency. This needs to be done during the development phase so that alternative strategies can be implemented prior to process module integration. Therefore, work is ongoing to characterize stress related wafer deformation on overlay performance after every process step. This work will allow to evaluate and minimize non-scanner related grid error which will contribute to total overlay.
Several DP specific metrology challenges were identified. Accurate analysis of the error contributions at every DP process step demands a clear separation of the DP population 1 and 2 measurements. Metrology techniques or algorithms to precisely acquire the correct measurement target are needed. Also, metrology techniques for CD and overlay need to be developed for 32nm node and towards 22nm node. This is being done for CD scanning electron microscopy (SEM) and other metrology techniques including measurement target design, target placement, sampling plan.