Scaling-driven nanoelectronics
The mission of IMEC's CMOS process development and integration programs is to perform focused research for technology nodes at least two generations ahead of manufacturing, and thus at least one generation ahead of development. While the industry is working to put the 45nm technology node into production, research at IMEC is shifting to the 22nm node and beyond. In 2007, in response to the changing semiconductor landscape, IMEC has increased its focus on design and memory technologybringing its logic and memory research (flash and DRAM) on equal footing in the (sub-)32nm CMOS research platform.
Transistor scaling no longer automatically results in reduced costs and power consumption. Issues such as power leakage and process variability are challenging Moore's law. Maintaining the transistor performance at shrinking dimensions calls for new materials, new transistor architectures, and advanced lithography techniques.
In 2007, the highlights of IMEC's research included the introduction of new materials (high-k dielectrics, metal gates, low-k interconnects), new device concepts (ultra-shallow junctions, strain engineering, FinFETs), new lithography techniques (EUV, double patterning), and ultra-clean processing.
To prepare for the era beyond CMOS scaling, or even beyond silicon, and to ensure the continued success of the IC industry, IMEC also studies high-mobility substrates such as germanium and III-V materials. And looking even further in the future, IMEC explores the possibilities of carbon nanotubes, grapheme, and spintronics.
For its research on CMOS-based transistor scaling, IMEC strongly collaborates with world-leading IC manufacturers, foundries, and equipment and material suppliers.
Under its program-driven business model, many of the top IC-manufacturers build on IMEC for providing research know- how as critical input to their process development activities.