NOSCE MEMORIAS

SPECIFIC TARGETED RESEARCH OR INNOVATION PROJECT

SIXTH FRAMEWORK PROGRAMME

PRIORITY 2

INFORMATION SOCIETY TECHNOLOGIES

1. Project Summary

With the scaling of successive generations of CMOS technologies, further scaling of the different memory types (DRAM, Flash, FeRAM, MRAM) is no longer feasible due to physical and/or cost limitations. Furthermore, the processes for various types of memories on CMOS are increasing in complexity and as a result becoming mutually exclusive. This threatens the further scaling of systems-on-chip, on which several memory types (SRAM, DRAM, Flash, …) often must be integrated simultaneously.

As a result, there is a very strong driving force to develop novel memory concepts world-wide. The purpose is to find materials and concepts that re-unite the following 5 major characteristics :

1. scalable for at least several generations from the 45 nm CMOS node on;
2. non-volatile;
3. fast (ns and less) intrinsic switching mechanism;
4. the technology and materials must be compatible with present-day and future generations of CMOS
5. a single and simple technological platform to produce a single unified memory cell should allow to generate memories with various characteristics by variation of the memory architecture in which such cell is embedded.

The purpose of the research in the present project is to assess the performance and validate the possibility to implement cross-point memory cells based on these two options in standard backend-of-line CMOS processes. The proposed research comprises:

1. Optimizing material systems and cell concepts for novel non-volatile memories
2. Improving the fundamental understanding of the switching mechanisms to achieve maximum performance of non-volatile memory cells (endurance, switching speed, …)
3. Demonstrating the scalability down to feature sizes < 90 nm.
4. Demonstrating the new cell concepts with cell size down to 4 F² and with programmable active memory area down to 1 F², where F is half the minimum metal pitch
5. Defining the reliability specifications for these memories.
6. Verifying the compatibility of the new materials and cells with standard CMOS backend-of-line processes, including an initial compatibility / contamination study of CMOS by the new materials

The consortium consists of the minimum set of required partners for this highly targeted and ambitious research plan. Philips and STMicroelectronics have, for different applications, performed several years of research to screen and preselect novel candidate memory cells and suitable materials. This strong background allows the consortium to focus on a limited number of two most promising options: one organic charge transfer material cell, and one ferro-electric Schottky barrier memory cell. IMEC provides the integration of the cells into CMOS backend-of-line. The Polish Academy of Sciences has yearlong experience in physics and analysis of semiconductor materials and devices, and will use its background to provide understanding of fundamental switching phenomena.

2. Project objectives

As the scaling of CMOS technology proceeds, there is an ever-increasing urge to simplify random-access memory technologies, on the one hand, and to unify the different technologies as much as possible, on the other hand. The purposes of this simplification and this unification are to allow memories to scale further at the pace of CMOS, and to ultimately decrease the system cost.

The simplification stands in contrast to the complexity of today’s technologies, especially when projected to future CMOS nodes (65 nm and beyond). Unification refers to the fact that today’s memory concepts tend to become more complex on their own, and less compatible with each other.

Novel memory technologies based on new materials will be a technical necessity for certain products at the 45 nm CMOS node, and increase in importance beyond. The novel memory concepts must therefore allow scaling, such as not to be limited in terms of density compared to the CMOS technology.

Ideally, the ultimate „unified memory“ aims at replacing conventional embedded and stand-alone memories, i.e. native SRAM and DRAM, as well as the embedded DRAM, Flash and EEPROM memories in a CMOS process. However, even if all memories cannot be united into a single type of memory, the target should be to at least unify the technologies to produce the fundamental memory cell. This unified technology platform offers the possibility to provide different versions with various balances of speed, density, endurance, etc… depending on the application at minimal costs and efforts.

Even if this new memory platform is targeted to solve issues with conventional memories expected at feature sizes below 50 nm, the technology base may be also used at larger dimensions due to additional features compared to today´s standard memories, e.g. non-volatility, low voltage, small cell size, and reduced cost.

The targeted work focuses on the concept of the cell. The purpose is to demonstrate all essential features of a unified memory cell, this is a fundamental cross-point cell concept that is scalable, has low complexity, is non-volatile and in addition allows integration into different memory architectures, that can lead to different memory products and applications. The architectures that should be supported are the cross-point memory (Fig. 1a), the via-hole cross-point memory (Fig. 1b) and an active matrix memory (Fig. 1c). The possibility to be used in such diverse architectures corresponds to fulfilling the criteria of “Unification” and “Simplification” set above.

Fig 1c Active matrix memory (PE: programmable element in via hole)

The investigations will be performed on a limited set of two pre-selected new memory materials classes. Both are of the switchable-resistance type. The materials systems that have been pre-selected are :

• Organic Charge-Transfer Materials (CT materials)
• A ferro-electric Schottky diode

The pre-selection has been done by screening a large number of proposals as well as by a few years of laboratory tests at the sites of the proposers, on the basis of the following criteria:

• the potential for integration within the back-end-of-line of contemporary and future CMOS nodes
• preliminary information, obtained on single cells, concerning the performance: power consumption, voltage levels, current levels, switching speed, endurance
• the potential for scaling
• the potential density, including, where appropriate, the potential of 3D stacking

The outcome of the project will be a recommendation of new materials, demonstrated concepts and corresponding integration schemes for scalable unified memories for the CMOS generations of 45-nm and beyond. Once available, the usage is possible for larger dimensions too. The project outcome will include appropriate integration schemes using standard Si process steps. This outcome is the necessary base for product demonstrators to prove the competitive advantages of these new memory devices.

Fig. 2 cell size and memory element size in crosspoint array concept

Objectives 1,2,3 and 5, if achieved simultaneously, correspond to attaining the basic technology for a unified scalable memory. With a unified memory, several applications can be covered: Novel Systems on Chip as well as mass-storage products for the mass markets. The crosspoint architecture has the versatility to allow the different configurations that are shown in Fig. 1:

• A cross-point array architecture (Fig. 1a), in which every memory cell is located simply at the cross-point of two perpendicular wires, and where the overlapping area forms the memory area. This architecture will offer the highest integration density and the simplest and lowest cost technology but not the ultimate speed because of the electrical limitations of the cross-point array. This architecture allows stacking of more than one layer of memory arrays, to further increase the integration density. It is suited for all stand-alone and embedded applications where high densities (1 Gbit or more per memory layer) at moderate speed is needed, thus not only as potential DRAM replacement, but also as low-cost mass storage memory.
• A via-hole array architecture (Fig. 1b), in which, in addition to the two above wires, an intermetal dielectric layer is positioned with a via hole at the overlaps. The memory material fills the via holes either completely or partially. This configuration offers the second highest integration density but is already more complex. It is expected to provide possibly higher speed because of less cross-talk. This architecture too allows 3-D stacking to further increase the integration density, and is therefore also an option suited for a high-density stand-alone memory.
• An active matrix architecture, (Fig. 1c). In this architecture, the memory will have the fastest speed, but obviously, the requirement to have one transistor per memory cell results in a smaller integration density.  This type of memory is suited for replacement of fast memories (like SRAM), where access time is most crucial. It should be noted that the integration with an access transistor requires front-end CMOS to be realized, which is not the intention in this project.

The above applications have different requirements in terms of integration compatibility, endurance, reliability, access time, power supply voltage, etc… For the above-described potential applications, the required specifications for these parameters will be determined in the first three months of the project, and the performance of the proposed cell concepts and material systems will subsequently (at month 12 and 18) be evaluated against these specifications.

3. Participant list

*CO = Coordinator
  CR = Contractor