NANO-RF Introduction

CMOS scaling is the engine of the continuous improvement of digital applications. It has also been demonstrated that CMOS also offers great potential for very high speed or very low power wireless and wireline applications. This potential, together with the high levels of integration that are typical for CMOS technology, and the cost per square mm, allows RF CMOS to compete with SiGe(C) bipolar and BiCMOS and III-V (GaAs, InP) as the technology of choice for new communication demands in volume production.

However, at the same time, limitations start to appear, especially with respect to Vdd scaling, and loss of analog performance with the introduction of new materials. The 45nm node (and beyond) is not well established for digital CMOS, which makes it more difficult to assess the analog/RF performance on the level of basic building blocks.

The IST NANO-RF project is a European Specific Targeted Research Project (STREP) in the frame of the Sixt Framework Programme PRIORITY 2 (Information Society Technologies) that adresses the challenges of the CMOS downscaling to 45nm and beyond, for analog and RF applications.