EMMA
Emerging Materials for Mass-storage Architectures 

SPECIFIC TARGETED RESEARCH OR INNOVATION PROJECT

SIXTH FRAMEWORK PROGRAM
PRIORITY 2
INFORMATION SOCIETY TECHNOLOGIES

1. Project Summary

This project will investigate the feasibility of emerging new non-volatile memory concepts based on resistive-switching materials for enabling new mass-storage memory systems. These new memory concepts allow integration of the memory element in contact and interconnect structures resulting in very small memory cells and even offer the possibility of 3-D memory layer stacking. These new memory solutions are needed for the sub-32nm integration technology nodes where current memory concepts will no longer scale.
The program will study high-density resistive switching non-volatile memories, including binary resistive switching oxides and CuTCNQ. Focus will be on concept scalability, based on gained understanding of the physical operation concepts. Investigation will further include cell integration aspects, reliability assessment, and memory architectures.

2. Project objectives

The objective of the EMMA project is the investigation of new solutions for massive non-volatile data storage solid-state memories. The achievement of this objective would represent a complete breakthrough in the field of memory devices and related production technologies.

• The final objectives of the project are:
• Understanding of the memory switching effect and of the electrode materials impact;
• Demonstration of the cell functionality with the proposed active material, showing superior electrical performances compared to the existing and also the emerging non-volatile memory concepts;
• Assessment of the manufacturability of the new proposed active materials and electrodes; 
• Identification of the array architectures, programming and reading conditions, reliability issues and scalability of the proposed approach for mass-storage applications beyond the 32nm technological nod

Research activity in EMMA will address the technical challenges covering all the issues from materials selection to the technologically-significant fabrication of memory cell structures to the final investigation of the system requirements, performances, and scaling capabilities.

To set a guideline as well as an evaluation reference for the development work in the EMMA project, a list of target specifications (both on device/cell level as well as on final memory array level) should be defined. While a more detailed and specific list of target specifications will be generated  in the beginning of the project, we can already consider the rather general specification targets for non-volatile memories (See Table 1), as well as a preliminary draft of a number of more specific specifications for the development in the EMMA project (See Table 2).

Table 1: General target specification for both high-density (stand alone) memories, and for high-performance (embedded) memories

Table 2: Preliminary and limited list of targeted electrical parameter values for development work in EMMA.

Specific R&D targets of EMMA will include:

On the materials side:
- Study of the mechanisms: although some experimental results showed the suitability of the proposed investigated material for non-volatile storage, a clear understanding of the memory mechanisms is still lacking. CuTCNQ and binary oxides will be then deposited on suitable test structure with different electrode materials, and their properties will be investigated to understand how the switching effect occurs and the role of the electrode materials.
- Moreover, acceptance criteria for the proposed materials will be checked, according to the target parameters reported in Table 2 and the more extended specifications that will be specified.

On the cell architecture:
- Suitable cell architecture to exploit the memory capability of the selected material will be fabricated mainly on a 90nm CMOS technology platform with the aim of achieving a final demonstration in 65nm technology. The cell structure will be selected targeting an 8F2 cell size and suitable to be scaled below the 32nm technological node.
- Both the programming performance and the reliability characteristics will be optimized to reach the targeted values reported in Table 2.
 
On the system architecture:
- identification of the array architectures for mass-storage memories, based on the materials and cell concepts developed. Architecture definition will include not only layout, programming and reading conditions, but it will take also in consideration reliability issues, parasitic paths, parasitic programming and scalability of the proposed approach.

The final outcome of the project will be the demonstration of resistance switching cells compliant with the values reported in Table 2, (that will be more detailed and extended). The manufacturability of devices with the selected materials will be addressed performing compatibility tests with the CMOS line. A suitable memory architecture will be identified (including programming and reading concepts, cell selection and isolation,) and the potential scaling issues will be addressed to demonstrate the scalability of the proposed technology beyond the 32nm technological node.

To this purpose, in this proposal, next activities are defined that are structures in 5 different Work Packages:
In WP1, Memory materials and electrode technology, focus is on the development of the material technology. The deposition process and material characteristics of these materials will be developed, characterized and optimized in this task. As the basic memory element of these new non-volatile memories is a metal-resistive-metal (MRM) structure, besides the memory material itself, different electrode materials for bottom and top electrode will be evaluated as well.
WP2, Cell integration technology, focuses on the fabrication of test structures and demonstrators. It involves test structure design, fabrication of pre-processed wafers for memory material deposition, and post-processing.
In WP3, Electric and reliability characterization, performance characterization of the test structures made in a combined effort of WP1 and WP2 will be done. This will provide crucial information on the suitability of these materials for their intended non-volatile memory application. The electrical characteristics will also be used for establishing a compact model of the memory element.
WP4, Physical mechanisms, modeling and scaling, will probe at the underlying mechanisms of the memory switching process, leading to a physical modeling and enabling evaluating basic scaling potential.
WP5, System architecture, will define array architectures for the mass-storage memories based on the studied materials and cell concepts.

The next figure shows how these final objectives are realized in the project by these different Work Package activities:

Figure 1: Schematic outline of project structure for realizing the final objectives.

3. Participant list

*CO = Coordinator
CR = Contractor